ppc_860.h

ecos为实时嵌入式操作系统

#ifndef CYGONCE_PPC_860_H
#define CYGONCE_PPC_860_H

//=============================================================================
//####UNSUPPORTEDBEGIN####
//
// -------------------------------------------
// This source file has been contributed to eCos/Cygnus. It may have been
// changed slightly to provide an interface consistent with those of other 
// files.
//
// The functionality and contents of this file is supplied "AS IS"
// without any form of support and will not necessarily be kept up
// to date by Cygnus.
//
// The style of programming used in this file may not comply with the
// eCos programming guidelines. Please do not use as a base for other
// files.
//
// All inquiries about this file, or the functionality provided by it,
// should be directed to the 'ecos-discuss' mailing list (see
// http://sourceware.cygnus.com/ecos/intouch.html for details).
//
// Contributed by: Kevin Hester <[e-mail]>
// Maintained by:  <Unmaintained>
// See also:
//   Motorola's "Example Software Initializing the SMC as a UART" package 
//   (smc2.zip) at:
//    http://www.mot.com/SPS/RISC/netcomm/tools/index.html#MPC860_table
// -------------------------------------------
//
//####UNSUPPORTEDEND####
//=============================================================================

#include <cyg/infra/cyg_type.h>

/******************************************************************************
*
* Definitions of Parameter RAM entries for each peripheral and mode
*
******************************************************************************/

/*---------------------------------------------------------------------------*/
/*      HDLC parameter RAM (SCC)                                             */
/*---------------------------------------------------------------------------*/

struct hdlc_pram 

{
       
   /*-------------------*/
   /* SCC parameter RAM */
   /*-------------------*/
   
   cyg_uint16   rbase;          /* RX BD base address */
   cyg_uint16   tbase;          /* TX BD base address */
   cyg_uint8       rfcr;                   /* Rx function code */
   cyg_uint8       tfcr;                   /* Tx function code */
   cyg_uint16   mrblr;          /* Rx buffer length */
   cyg_uint32      rstate;              /* Rx internal state */
   cyg_uint32      rptr;                   /* Rx internal data pointer */
   cyg_uint16   rbptr;          /* rb BD Pointer */
   cyg_uint16   rcount;         /* Rx internal byte count */
   cyg_uint32      rtemp;               /* Rx temp */
   cyg_uint32      tstate;              /* Tx internal state */
   cyg_uint32      tptr;                   /* Tx internal data pointer */
   cyg_uint16   tbptr;          /* Tx BD pointer */
   cyg_uint16   tcount;         /* Tx byte count */
   cyg_uint32      ttemp;               /* Tx temp */
   cyg_uint32      rcrc;                   /* temp receive CRC */
   cyg_uint32      tcrc;                   /* temp transmit CRC */
   
   /*-----------------------------*/
   /* HDLC specific parameter RAM */
   /*-----------------------------*/

   cyg_uint8       RESERVED1[4];        /* Reserved area */
   cyg_uint32      c_mask;                      /* CRC constant */
   cyg_uint32      c_pres;                      /* CRC preset */
   cyg_uint16   disfc;                  /* discarded frame counter */
   cyg_uint16   crcec;                  /* CRC error counter */
   cyg_uint16   abtsc;                  /* abort sequence counter */
   cyg_uint16   nmarc;                  /* nonmatching address rx cnt */
   cyg_uint16   retrc;                  /* frame retransmission cnt */
   cyg_uint16   mflr;                      /* maximum frame length reg */
   cyg_uint16   max_cnt;                   /* maximum length counter */
   cyg_uint16   rfthr;                  /* received frames threshold */
   cyg_uint16   rfcnt;                  /* received frames count */
   cyg_uint16   hmask;                  /* user defined frm addr mask */
   cyg_uint16   haddr1;                 /* user defined frm address 1 */
   cyg_uint16   haddr2;                 /* user defined frm address 2 */
   cyg_uint16   haddr3;                 /* user defined frm address 3 */
   cyg_uint16   haddr4;                 /* user defined frm address 4 */
   cyg_uint16   tmp;                       /* temp */
   cyg_uint16   tmp_mb;                 /* temp */
};


/*-------------------------------------------------------------------------*/
/*                       ASYNC HDLC parameter RAM (SCC)                                                  */
/*-------------------------------------------------------------------------*/

struct async_hdlc_pram 

{
       
   /*-------------------*/
   /* SCC parameter RAM */
   /*-------------------*/

   cyg_uint16   rbase;          /* RX BD base address */
   cyg_uint16   tbase;          /* TX BD base address */
   cyg_uint8       rfcr;                   /* Rx function code */
   cyg_uint8       tfcr;                   /* Tx function code */
   cyg_uint16   mrblr;          /* Rx buffer length */
   cyg_uint32      rstate;              /* Rx internal state */
   cyg_uint32      rptr;                   /* Rx internal data pointer */
   cyg_uint16   rbptr;          /* rb BD Pointer */
   cyg_uint16   rcount;         /* Rx internal byte count */
   cyg_uint32      rtemp;               /* Rx temp */
   cyg_uint32      tstate;              /* Tx internal state */
   cyg_uint32      tptr;                   /* Tx internal data pointer */
   cyg_uint16   tbptr;          /* Tx BD pointer */
   cyg_uint16   tcount;         /* Tx byte count */
   cyg_uint32   ttemp;          /* Tx temp */
   cyg_uint32      rcrc;                   /* temp receive CRC */
   cyg_uint32    tcrc;             /* temp transmit CRC */
         
   /*-----------------------------------*/
   /* ASYNC HDLC specific parameter RAM */
   /*-----------------------------------*/

   cyg_uint8       RESERVED2[4];        /* Reserved area */
   cyg_uint32      c_mask;                      /* CRC constant */
   cyg_uint32      c_pres;                      /* CRC preset */
   cyg_uint16   bof;                       /* begining of flag character */
   cyg_uint16   eof;                       /* end of flag character */
   cyg_uint16   esc;                       /* control escape character */
   cyg_uint8       RESERVED3[4];        /* Reserved area */
   cyg_uint16   zero;                      /* zero */
   cyg_uint8       RESERVED4[2];        /* Reserved area */
   cyg_uint16   rfthr;                  /* received frames threshold */
   cyg_uint8       RESERVED5[4];        /* Reserved area */
   cyg_uint32      txctl_tbl;           /* Tx ctl char mapping table */
   cyg_uint32      rxctl_tbl;           /* Rx ctl char mapping table */
   cyg_uint16   nof;                       /* Number of opening flags */
};


/*--------------------------------------------------------------------------*/
/*                    UART parameter RAM (SCC)                                                                 */
/*--------------------------------------------------------------------------*/

/*----------------------------------------*/
/* bits in uart control characters table  */
/*----------------------------------------*/

#define CC_INVALID      0x8000          /* control character is valid */
#define CC_REJ          0x4000          /* don't store char in buffer */
#define CC_CHAR         0x00ff          /* control character */

/*------*/
/* UART */
/*------*/

struct uart_pram 

{
   /*-------------------*/
   /* SCC parameter RAM */
   /*-------------------*/

   cyg_uint16   rbase;          /* RX BD base address */
   cyg_uint16   tbase;          /* TX BD base address */
   cyg_uint8       rfcr;                   /* Rx function code */
   cyg_uint8       tfcr;                   /* Tx function code */
   cyg_uint16   mrblr;          /* Rx buffer length */
   cyg_uint32      rstate;              /* Rx internal state */
   cyg_uint32      rptr;                   /* Rx internal data pointer */
   cyg_uint16   rbptr;          /* rb BD Pointer */
   cyg_uint16   rcount;         /* Rx internal byte count */
   cyg_uint32      rx_temp;        /* Rx temp */
   cyg_uint32      tstate;              /* Tx internal state */
   cyg_uint32      tptr;                   /* Tx internal data pointer */
   cyg_uint16   tbptr;          /* Tx BD pointer */
   cyg_uint16   tcount;         /* Tx byte count */
   cyg_uint32      ttemp;               /* Tx temp */
   cyg_uint32      rcrc;                   /* temp receive CRC */
   cyg_uint32      tcrc;                   /* temp transmit CRC */

   /*------------------------------*/
   /*   UART specific parameter RAM  */
   /*------------------------------*/

   cyg_uint8       RESERVED6[8];        /* Reserved area */
   cyg_uint16   max_idl;                   /* maximum idle characters */
   cyg_uint16   idlc;                      /* rx idle counter (internal) */
   cyg_uint16   brkcr;                  /* break count register */

   cyg_uint16   parec;                  /* Rx parity error counter */
   cyg_uint16   frmec;                  /* Rx framing error counter */
   cyg_uint16   nosec;                  /* Rx noise counter */
   cyg_uint16   brkec;                  /* Rx break character counter */
   cyg_uint16   brkln;                  /* Reaceive break length */
                                           
   cyg_uint16   uaddr1;                 /* address character 1 */
   cyg_uint16   uaddr2;                 /* address character 2 */
   cyg_uint16   rtemp;                  /* temp storage */
   cyg_uint16   toseq;                  /* Tx out of sequence char */
   cyg_uint16   cc[8];                  /* Rx control characters */
   cyg_uint16   rccm;                      /* Rx control char mask */
   cyg_uint16   rccr;                      /* Rx control char register */
   cyg_uint16   rlbc;                      /* Receive last break char */
};


/*---------------------------------------------------------------------------
*                    BISYNC parameter RAM (SCC)
*--------------------------------------------------------------------------*/

struct bisync_pram 

{
   /*-------------------*/
   /* SCC parameter RAM */
   /*-------------------*/

   cyg_uint16   rbase;          /* RX BD base address */
   cyg_uint16   tbase;          /* TX BD base address */
   cyg_uint8       rfcr;                   /* Rx function code */
   cyg_uint8       tfcr;                   /* Tx function code */
   cyg_uint16   mrblr;          /* Rx buffer length */
   cyg_uint32      rstate;              /* Rx internal state */
   cyg_uint32      rptr;                   /* Rx internal data pointer */
   cyg_uint16   rbptr;          /* rb BD Pointer */
   cyg_uint16   rcount;         /* Rx internal byte count */
   cyg_uint32      rtemp;               /* Rx temp */
   cyg_uint32      tstate;              /* Tx internal state */
   cyg_uint32      tptr;                   /* Tx internal data pointer */
   cyg_uint16   tbptr;          /* Tx BD pointer */
   cyg_uint16   tcount;         /* Tx byte count */
   cyg_uint32      ttemp;               /* Tx temp */
   cyg_uint32      rcrc;                   /* temp receive CRC */
   cyg_uint32      tcrc;                   /* temp transmit CRC */

   /*--------------------------------*/
   /*   BISYNC specific parameter RAM */
   /*--------------------------------*/

   cyg_uint8       RESERVED7[4];        /* Reserved area */
   cyg_uint32      crcc;                           /* CRC Constant Temp Value */
   cyg_uint16   prcrc;                  /* Preset Receiver CRC-16/LRC */
   cyg_uint16   ptcrc;                  /* Preset Transmitter CRC-16/LRC */
   cyg_uint16   parec;                  /* Receive Parity Error Counter */
   cyg_uint16   bsync;                  /* BISYNC SYNC Character */
   cyg_uint16   bdle;                      /* BISYNC DLE Character */
   cyg_uint16   cc[8];                  /* Rx control characters */
   cyg_uint16   rccm;                      /* Receive Control Character Mask */
};


/*-------------------------------------------------------------------------*/
/*             Transparent mode parameter RAM (SCC)                                                */
/*-------------------------------------------------------------------------*/

struct transparent_pram 

{
   /*--------------------*/
   /*   SCC parameter RAM */
   /*--------------------*/

   cyg_uint16   rbase;          /* RX BD base address */
   cyg_uint16   tbase;          /* TX BD base address */
   cyg_uint8       rfcr;                   /* Rx function code */
   cyg_uint8       tfcr;                   /* Tx function code */
   cyg_uint16   mrblr;          /* Rx buffer length */
   cyg_uint32      rstate;              /* Rx internal state */
   cyg_uint32      rptr;                   /* Rx internal data pointer */
   cyg_uint16   rbptr;          /* rb BD Pointer */
   cyg_uint16   rcount;         /* Rx internal byte count */
   cyg_uint32      rtemp;               /* Rx temp */
   cyg_uint32      tstate;              /* Tx internal state */
   cyg_uint32      tptr;                   /* Tx internal data pointer */
   cyg_uint16   tbptr;          /* Tx BD pointer */
   cyg_uint16   tcount;         /* Tx byte count */
   cyg_uint32      ttemp;               /* Tx temp */
   cyg_uint32      rcrc;                   /* temp receive CRC */
   cyg_uint32      tcrc;                   /* temp transmit CRC */

   /*-------------------------------------*/
   /*   TRANSPARENT specific parameter RAM */
   /*-------------------------------------*/

   cyg_uint32   crc_p;          /* CRC Preset */
   cyg_uint32   crc_c;          /* CRC constant */
};


/*-------------------------------------------------------------------------*/ 
/*                    Ethernet parameter RAM (SCC)                                                       */
/*-------------------------------------------------------------------------*/

struct ethernet_pram 

{
   /*--------------------*/
   /*   SCC parameter RAM */
   /*--------------------*/

   cyg_uint16   rbase;          /* RX BD base address */
   cyg_uint16   tbase;          /* TX BD base address */
   cyg_uint8       rfcr;                   /* Rx function code */
   cyg_uint8       tfcr;                   /* Tx function code */
   cyg_uint16   mrblr;          /* Rx buffer length */
   cyg_uint32      rstate;              /* Rx internal state */
   cyg_uint32      rptr;                   /* Rx internal data pointer */
   cyg_uint16   rbptr;          /* rb BD Pointer */
   cyg_uint16   rcount;         /* Rx internal byte count */
   cyg_uint32      rtemp;               /* Rx temp */
   cyg_uint32      tstate;              /* Tx internal state */
   cyg_uint32      tptr;                   /* Tx internal data pointer */
   cyg_uint16   tbptr;          /* Tx BD pointer */
   cyg_uint16   tcount;         /* Tx byte count */
   cyg_uint32      ttemp;               /* Tx temp */