ppc_regs.h

ecos为实时嵌入式操作系统

#ifndef CYGONCE_HAL_PPC_REGS_H
#define CYGONCE_HAL_PPC_REGS_H

//==========================================================================
//
//      ppc_regs.h
//
//      PowerPC CPU definitions
//
//==========================================================================
//####COPYRIGHTBEGIN####
//
// -------------------------------------------
// The contents of this file are subject to the Cygnus eCos Public License
// Version 1.0 (the "License"); you may not use this file except in
// compliance with the License.  You may obtain a copy of the License at
// http://sourceware.cygnus.com/ecos
// 
// Software distributed under the License is distributed on an "AS IS"
// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the
// License for the specific language governing rights and limitations under
// the License.
// 
// The Original Code is eCos - Embedded Cygnus Operating System, released
// September 30, 1998.
// 
// The Initial Developer of the Original Code is Cygnus.  Portions created
// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions.  All Rights Reserved.
// -------------------------------------------
//
//####COPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    jskov
// Contributors: jskov
// Date:         1999-02-19
// Purpose:      Provide PPC register definitions
// Description:  Provide PPC register definitions
//               The short difinitions (sans CYGARC_REG_) are exported only
//               if CYGARC_HAL_COMMON_EXPORT_CPU_MACROS is defined.
// Usage:
//               #include <cyg/hal/ppc_regs.h>
//               ...
//              
//
//####DESCRIPTIONEND####
//
//==========================================================================

#include <pkgconf/hal.h>

//--------------------------------------------------------------------------
// SPR access macros.
#define CYGARC_MTSPR(_spr_, _v_) \
    asm volatile ("mtspr %0, %1;" :: "I" (_spr_), "r" (_v_));
#define CYGARC_MFSPR(_spr_, _v_) \
    asm volatile ("mfspr %0, %1;" : "=r" (_v_) : "I" (_spr_));

//--------------------------------------------------------------------------
// TB access macros.
#define CYGARC_MTTB(_tbr_, _v_) \
    asm volatile ("mttb %0, %1;" :: "I" (_tbr_), "r" (_v_));
#define CYGARC_MFTB(_tbr_, _v_) \
    asm volatile ("mftb %0, %1;" : "=r" (_v_) : "I" (_tbr_));

//--------------------------------------------------------------------------
// Generic Definitions
//--------------------------------------------------------------------------

//--------------------------------------------------------------------------
// Some SPRs
#define CYGARC_REG_DSISR    18
#define CYGARC_REG_DAR      19
#define CYGARC_REG_DEC      22
#define CYGARC_REG_SRR0     26
#define CYGARC_REG_SRR1     27
#define CYGARC_REG_SPRG0   272
#define CYGARC_REG_SPRG1   273
#define CYGARC_REG_SPRG2   274
#define CYGARC_REG_SPRG3   275
#define CYGARC_REG_PVR     287

#define CYGARC_REG_TBL_W   284
#define CYGARC_REG_TBU_W   285

#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
#define DSISR      CYGARC_REG_DSISR
#define DAR        CYGARC_REG_DAR
#define DEC        CYGARC_REG_DEC
#define SRR0       CYGARC_REG_SRR0
#define SRR1       CYGARC_REG_SRR1
#define SPRG0      CYGARC_REG_SPRG0
#define SPRG1      CYGARC_REG_SPRG1
#define SPRG2      CYGARC_REG_SPRG2
#define SPRG3      CYGARC_REG_SPRG3
#define PVR        CYGARC_REG_PVR

#define TBL_W      CYGARC_REG_TBL_W
#define TBU_W      CYGARC_REG_TBU_W
#endif

//--------------------------------------------------------------------------
// MSR bits
#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
#define MSR_LE          0x00000001      // little-endian mode enable
#define MSR_RI          0x00000002      // recoverable exception
#define MSR_DR          0x00000010      // data address translation
#define MSR_IR          0x00000020      // instruction address translation
#define MSR_IP          0x00000040      // exception prefix
#define MSR_FE1         0x00000100      // floating-point exception mode 1
#define MSR_BE          0x00000200      // branch trace enable
#define MSR_SE          0x00000400      // single-step trace enable
#define MSR_FE0         0x00000800      // floating-point exception mode 0
#define MSR_ME          0x00001000      // machine check enable
#define MSR_FP          0x00002000      // floating-point available
#define MSR_PR          0x00004000      // privilege level
#define MSR_EE          0x00008000      // external interrupt enable
#define MSR_ILE         0x00010000      // exception little-endian mode
#define MSR_POW         0x00040000      // power management enable
#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS

//--------------------------------------------------------------------------
// Time Base Registers
#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
#define TBL_R           268
#define TBU_R           269
#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS

//--------------------------------------------------------------------------
// MPC603 Specific Definitions
//--------------------------------------------------------------------------
#ifdef CYG_HAL_POWERPC_MPC603

//--------------------------------------------------------------------------
// Cache
#define CYGARC_REG_HID0   1008

#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
#define HID0       CYGARC_REG_HID0
#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS


//--------------------------------------------------------------------------
// BATs
#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
#define IBAT0U          528
#define IBAT0L          529
#define IBAT1U          530
#define IBAT1L          531
#define IBAT2U          532
#define IBAT2L          533
#define IBAT3U          534
#define IBAT3L          535

#define DBAT0U          536
#define DBAT0L          537
#define DBAT1U          538
#define DBAT1L          539
#define DBAT2U          540
#define DBAT2L          541
#define DBAT3U          542
#define DBAT3L          543

#define UBAT_BEPIMASK   0xfffe0000      // effective address mask
#define UBAT_BLMASK     0x00001ffc      // block length mask
#define UBAT_VS         0x00000002      // supervisor mode valid bit
#define UBAT_VP         0x00000001      // problem mode valid bit

#define LBAT_BRPNMASK   0xfffe0000      // real address mask
#define LBAT_W          0x00000040      // write-through
#define LBAT_I          0x00000020      // caching-inhibited
#define LBAT_M          0x00000010      // memory coherence
#define LBAT_G          0x00000008      // guarded

#define LBAT_PP_NA      0x00000000      // no access
#define LBAT_PP_RO      0x00000001      // read-only
#define LBAT_PP_RW      0x00000002      // read/write
#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS

#endif // ifdef CYG_HAL_POWERPC_MPC603

//--------------------------------------------------------------------------
// MPC8xx Generic Definitions
//--------------------------------------------------------------------------
#ifdef CYG_HAL_POWERPC_MPC8xx

//--------------------------------------------------------------------------
// Instruction cache control.
#define CYGARC_REG_IC_CST          560
#define CYGARC_REG_IC_ADR          561
#define CYGARC_REG_IC_DAT          562

#define CYGARC_REG_IC_CMD_CE       0x02000000      // cache enable
#define CYGARC_REG_IC_CMD_CD       0x04000000      // cache disable
#define CYGARC_REG_IC_CMD_LL       0x06000000      // load & lock
#define CYGARC_REG_IC_CMD_UL       0x08000000      // unlock line
#define CYGARC_REG_IC_CMD_UA       0x0a000000      // unlock all
#define CYGARC_REG_IC_CMD_IA       0x0c000000      // invalidate all

#define CYGARC_REG_IC_ADR_SETID_SHIFT 4            // set id is bits 21-27
#define CYGARC_REG_IC_ADR_WAY0     0x00000000      // select way0
#define CYGARC_REG_IC_ADR_WAY1     0x00001000      // select way1

#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
#define IC_CST          CYGARC_REG_IC_CST
#define IC_ADR          CYGARC_REG_IC_ADR
#define IC_DAT          CYGARC_REG_IC_DAT

#define IC_CMD_CE       CYGARC_REG_IC_CMD_CE
#define IC_CMD_CD       CYGARC_REG_IC_CMD_CD
#define IC_CMD_LL       CYGARC_REG_IC_CMD_LL
#define IC_CMD_UL       CYGARC_REG_IC_CMD_UL
#define IC_CMD_UA       CYGARC_REG_IC_CMD_UA
#define IC_CMD_IA       CYGARC_REG_IC_CMD_IA

#define IC_ADR_SETID_SHIFT CYGARC_REG_IC_ADR_SETID_SHIFT
#define IC_ADR_WAY0        CYGARC_REG_IC_ADR_WAY0
#define IC_ADR_WAY1        CYGARC_REG_IC_ADR_WAY1
#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS

//--------------------------------------------------------------------------
// Data cache control.
#define CYGARC_REG_DC_CST          568
#define CYGARC_REG_DC_ADR          569
#define CYGARC_REG_DC_DAT          570

#define CYGARC_REG_DC_CMD_CE       0x02000000      // cache enable
#define CYGARC_REG_DC_CMD_CD       0x04000000      // cache disable
#define CYGARC_REG_DC_CMD_LL       0x06000000      // lock line
#define CYGARC_REG_DC_CMD_UL       0x08000000      // unlock line
#define CYGARC_REG_DC_CMD_UA       0x0a000000      // unlock all
#define CYGARC_REG_DC_CMD_IA       0x0c000000      // invalidate all
#define CYGARC_REG_DC_CMD_FL       0x0e000000      // flush line
#define CYGARC_REG_DC_CMD_SW       0x01000000      // set writethrough
#define CYGARC_REG_DC_CMD_CW       0x03000000      // clear writethrough
#define CYGARC_REG_DC_CMD_SS       0x05000000      // set little endian swap
#define CYGARC_REG_DC_CMD_CS       0x07000000      // clear little endian swap