hal_intr.h

ecos为实时嵌入式操作系统

#ifndef CYGONCE_HAL_INTR_H
#define CYGONCE_HAL_INTR_H

//==========================================================================
//
//      hal_intr.h
//
//      HAL Interrupt and clock support
//
//==========================================================================
//####COPYRIGHTBEGIN####
//
// -------------------------------------------
// The contents of this file are subject to the Cygnus eCos Public License
// Version 1.0 (the "License"); you may not use this file except in
// compliance with the License.  You may obtain a copy of the License at
// http://sourceware.cygnus.com/ecos
// 
// Software distributed under the License is distributed on an "AS IS"
// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the
// License for the specific language governing rights and limitations under
// the License.
// 
// The Original Code is eCos - Embedded Cygnus Operating System, released
// September 30, 1998.
// 
// The Initial Developer of the Original Code is Cygnus.  Portions created
// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions.  All Rights Reserved.
// -------------------------------------------
//
//####COPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    nickg
// Contributors: nickg, jskov,
//               jlarmour
// Date:         1999-02-19
// Purpose:      Define Interrupt support
// Description:  The macros defined here provide the HAL APIs for handling
//               interrupts and the clock.
//              
// Usage:
//               #include <cyg/hal/hal_intr.h>
//               ...
//              
//
//####DESCRIPTIONEND####
//
//==========================================================================

#include <pkgconf/hal.h>

#include <cyg/infra/cyg_type.h>

#include <cyg/hal/ppc_regs.h>           // register definitions
#include <cyg/hal/hal_io.h>             // io macros
#include <cyg/infra/cyg_ass.h>          // CYG_FAIL

//--------------------------------------------------------------------------
// PowerPC exception vectors. These correspond to VSRs and are the values
// to use for HAL_VSR_GET/SET

#define CYGNUM_HAL_VECTOR_RESERVED_0        0
#define CYGNUM_HAL_VECTOR_RESET             1
#define CYGNUM_HAL_VECTOR_MACHINE_CHECK     2
#define CYGNUM_HAL_VECTOR_DSI               3
#define CYGNUM_HAL_VECTOR_ISI               4
#define CYGNUM_HAL_VECTOR_INTERRUPT         5
#define CYGNUM_HAL_VECTOR_ALIGNMENT         6
#define CYGNUM_HAL_VECTOR_PROGRAM           7
#define CYGNUM_HAL_VECTOR_FP_UNAVAILABLE    8
#define CYGNUM_HAL_VECTOR_DECREMENTER       9
#define CYGNUM_HAL_VECTOR_RESERVED_A        10
#define CYGNUM_HAL_VECTOR_RESERVED_B        11
#define CYGNUM_HAL_VECTOR_SYSTEM_CALL       12
#define CYGNUM_HAL_VECTOR_TRACE             13
#define CYGNUM_HAL_VECTOR_FP_ASSIST         14

#define CYGNUM_HAL_VSR_MIN                   CYGNUM_HAL_VECTOR_RESERVED_0
#define CYGNUM_HAL_VSR_MAX                   CYGNUM_HAL_VECTOR_FP_ASSIST
#define CYGNUM_HAL_VSR_COUNT                 ( CYGNUM_HAL_VSR_MAX + 1 )

// The decoded interrupts.
// Define decrementer as the first interrupt since it is guaranteed to
// be defined on all PowerPCs. External may expand into several interrupts
// depending on interrupt controller capabilities.
#define CYGNUM_HAL_INTERRUPT_DECREMENTER     0
#define CYGNUM_HAL_INTERRUPT_EXTERNAL        1

// CYGNUM_HAL_ISR_COUNT must match CYG_ISR_TABLE_SIZE defined in vectors.S.
#define CYGNUM_HAL_ISR_MIN                   CYGNUM_HAL_INTERRUPT_DECREMENTER
#define CYGNUM_HAL_ISR_MAX                   CYGNUM_HAL_INTERRUPT_EXTERNAL
#define CYGNUM_HAL_ISR_COUNT                 ( CYGNUM_HAL_ISR_MAX + 1 )

// Exception vectors. These are the values used when passed out to an
// external exception handler using cyg_hal_deliver_exception()

#define CYGNUM_HAL_EXCEPTION_RESERVED_0      CYGNUM_HAL_VECTOR_RESERVED_0
#define CYGNUM_HAL_EXCEPTION_MACHINE_CHECK   CYGNUM_HAL_VECTOR_MACHINE_CHECK
#define CYGNUM_HAL_EXCEPTION_DATA_ACCESS     CYGNUM_HAL_VECTOR_DSI
#define CYGNUM_HAL_EXCEPTION_CODE_ACCESS     CYGNUM_HAL_VECTOR_ISI
#define CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_ACCESS  \
           CYGNUM_HAL_VECTOR_ALIGNMENT
#define CYGNUM_HAL_EXCEPTION_FPU_NOT_AVAIL   CYGNUM_HAL_VECTOR_FP_UNAVAILABLE
#define CYGNUM_HAL_EXCEPTION_RESERVED_A      CYGNUM_HAL_VECTOR_RESERVED_A
#define CYGNUM_HAL_EXCEPTION_RESERVED_B      CYGNUM_HAL_VECTOR_RESERVED_B
#define CYGNUM_HAL_EXCEPTION_SYSTEM_CALL     CYGNUM_HAL_VECTOR_SYSTEM_CALL
#define CYGNUM_HAL_EXCEPTION_TRACE           CYGNUM_HAL_VECTOR_TRACE
#define CYGNUM_HAL_EXCEPTION_FP_ASSIST       CYGNUM_HAL_VECTOR_FP_ASSIST

// decoded exception vectors
#define CYGNUM_HAL_EXCEPTION_TRAP                     (-1)
#define CYGNUM_HAL_EXCEPTION_PRIVILEGED_INSTRUCTION   (-2)
#define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION      (-3)
#define CYGNUM_HAL_EXCEPTION_FPU                      (-4)

#define CYGNUM_HAL_EXCEPTION_MIN             CYGNUM_HAL_EXCEPTION_FPU
#define CYGNUM_HAL_EXCEPTION_MAX             CYGNUM_HAL_VECTOR_FP_ASSIST
#define CYGNUM_HAL_EXCEPTION_COUNT           \
                 ( CYGNUM_HAL_EXCEPTION_MAX - CYGNUM_HAL_EXCEPTION_MIN + 1 )


#ifdef CYG_HAL_POWERPC_MPC8xx
// Additional exceptions on the MPC8xx
#define CYGNUM_HAL_VECTOR_RESERVED_F         15
#define CYGNUM_HAL_VECTOR_SW_EMUL            16
#define CYGNUM_HAL_VECTOR_ITLB_MISS          17
#define CYGNUM_HAL_VECTOR_DTLB_MISS          18
#define CYGNUM_HAL_VECTOR_ITLB_ERROR         19
#define CYGNUM_HAL_VECTOR_DTLB_ERROR         20
#define CYGNUM_HAL_VECTOR_RESERVED_15        21
#define CYGNUM_HAL_VECTOR_RESERVED_16        22
#define CYGNUM_HAL_VECTOR_RESERVED_17        23
#define CYGNUM_HAL_VECTOR_RESERVED_18        24
#define CYGNUM_HAL_VECTOR_RESERVED_19        25
#define CYGNUM_HAL_VECTOR_RESERVED_1A        26
#define CYGNUM_HAL_VECTOR_RESERVED_1B        27
#define CYGNUM_HAL_VECTOR_DATA_BP            28
#define CYGNUM_HAL_VECTOR_INSTRUCTION_BP     29
#define CYGNUM_HAL_VECTOR_PERIPHERAL_BP      30
#define CYGNUM_HAL_VECTOR_NMI                31

#define CYGNUM_HAL_EXCEPTION_RESERVED_F      CYGNUM_HAL_VECTOR_RESERVED_F
#define CYGNUM_HAL_EXCEPTION_SW_EMUL         CYGNUM_HAL_VECTOR_SW_EMUL
#define CYGNUM_HAL_EXCEPTION_CODE_TLBMISS_ACCESS  CYGNUM_HAL_VECTOR_ITLB_MISS
#define CYGNUM_HAL_EXCEPTION_DATA_TLBMISS_ACCESS  CYGNUM_HAL_VECTOR_DTLB_MISS
#define CYGNUM_HAL_EXCEPTION_CODE_TLBERROR_ACCESS \
               CYGNUM_HAL_VECTOR_ITLB_ERROR
#define CYGNUM_HAL_EXCEPTION_DATA_TLBERROR_ACCESS \
           CYGNUM_HAL_VECTOR_DTLB_ERROR
#define CYGNUM_HAL_EXCEPTION_RESERVED_15     CYGNUM_HAL_VECTOR_RESERVED_15
#define CYGNUM_HAL_EXCEPTION_RESERVED_16     CYGNUM_HAL_VECTOR_RESERVED_16
#define CYGNUM_HAL_EXCEPTION_RESERVED_17     CYGNUM_HAL_VECTOR_RESERVED_17
#define CYGNUM_HAL_EXCEPTION_RESERVED_18     CYGNUM_HAL_VECTOR_RESERVED_18
#define CYGNUM_HAL_EXCEPTION_RESERVED_19     CYGNUM_HAL_VECTOR_RESERVED_19
#define CYGNUM_HAL_EXCEPTION_RESERVED_1A     CYGNUM_HAL_VECTOR_RESERVED_1A
#define CYGNUM_HAL_EXCEPTION_RESERVED_1B     CYGNUM_HAL_VECTOR_RESERVED_1B
#define CYGNUM_HAL_EXCEPTION_DATA_BP         CYGNUM_HAL_VECTOR_DATA_BP
#define CYGNUM_HAL_EXCEPTION_INSTRUCTION_BP  CYGNUM_HAL_VECTOR_INSTRUCTION_BP
#define CYGNUM_HAL_EXCEPTION_PERIPHERAL_BP   CYGNUM_HAL_VECTOR_PERIPHERAL_BP
#define CYGNUM_HAL_EXCEPTION_NMI             CYGNUM_HAL_VECTOR_NMI

#undef  CYGNUM_HAL_EXCEPTION_MAX
#define CYGNUM_HAL_EXCEPTION_MAX             CYGNUM_HAL_EXCEPTION_NMI

// The first level of external interrupts
#define CYGNUM_HAL_INTERRUPT_SIU_IRQ0            1
#define CYGNUM_HAL_INTERRUPT_SIU_LVL0            2
#define CYGNUM_HAL_INTERRUPT_SIU_IRQ1            3
#define CYGNUM_HAL_INTERRUPT_SIU_LVL1            4
#define CYGNUM_HAL_INTERRUPT_SIU_IRQ2            5
#define CYGNUM_HAL_INTERRUPT_SIU_LVL2            6
#define CYGNUM_HAL_INTERRUPT_SIU_IRQ3            7
#define CYGNUM_HAL_INTERRUPT_SIU_LVL3            8
#define CYGNUM_HAL_INTERRUPT_SIU_IRQ4            9
#define CYGNUM_HAL_INTERRUPT_SIU_LVL4           10
#define CYGNUM_HAL_INTERRUPT_SIU_IRQ5           11
#define CYGNUM_HAL_INTERRUPT_SIU_LVL5           12
#define CYGNUM_HAL_INTERRUPT_SIU_IRQ6           13
#define CYGNUM_HAL_INTERRUPT_SIU_LVL6           14
#define CYGNUM_HAL_INTERRUPT_SIU_IRQ7           15
#define CYGNUM_HAL_INTERRUPT_SIU_LVL7           16

// Further decoded interrups
#define CYGNUM_HAL_INTERRUPT_SIU_TB_A           17
#define CYGNUM_HAL_INTERRUPT_SIU_TB_B           18
#define CYGNUM_HAL_INTERRUPT_SIU_PIT            19
#define CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC        20
#define CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR        21
#define CYGNUM_HAL_INTERRUPT_SIU_PCMCIA_A_IRQ   22
#define CYGNUM_HAL_INTERRUPT_SIU_PCMCIA_A_CHLVL 23
#define CYGNUM_HAL_INTERRUPT_SIU_PCMCIA_B_IRQ   24
#define CYGNUM_HAL_INTERRUPT_SIU_PCMCIA_B_CHLVL 25
#define CYGNUM_HAL_INTERRUPT_SIU_CPM            26

// Even further...
#define CYGNUM_HAL_INTERRUPT_CPM_PC15           27
#define CYGNUM_HAL_INTERRUPT_CPM_SCC1           28
#define CYGNUM_HAL_INTERRUPT_CPM_SCC2           29
#define CYGNUM_HAL_INTERRUPT_CPM_SCC3           30
#define CYGNUM_HAL_INTERRUPT_CPM_SCC4           31
#define CYGNUM_HAL_INTERRUPT_CPM_PC14           32
#define CYGNUM_HAL_INTERRUPT_CPM_TIMER1         33
#define CYGNUM_HAL_INTERRUPT_CPM_PC13           34
#define CYGNUM_HAL_INTERRUPT_CPM_PC12           35
#define CYGNUM_HAL_INTERRUPT_CPM_SDMA           36
#define CYGNUM_HAL_INTERRUPT_CPM_IDMA1          37
#define CYGNUM_HAL_INTERRUPT_CPM_IDMA2          38
#define CYGNUM_HAL_INTERRUPT_CPM_RESERVED_13    39
#define CYGNUM_HAL_INTERRUPT_CPM_TIMER2         40
#define CYGNUM_HAL_INTERRUPT_CPM_RISCTT         41
#define CYGNUM_HAL_INTERRUPT_CPM_I2C            42
#define CYGNUM_HAL_INTERRUPT_CPM_PC11           43
#define CYGNUM_HAL_INTERRUPT_CPM_PC10           44
#define CYGNUM_HAL_INTERRUPT_CPM_RESERVED_0D    45
#define CYGNUM_HAL_INTERRUPT_CPM_TIMER3         46
#define CYGNUM_HAL_INTERRUPT_CPM_PC9            47
#define CYGNUM_HAL_INTERRUPT_CPM_PC8            48
#define CYGNUM_HAL_INTERRUPT_CPM_PC7            49
#define CYGNUM_HAL_INTERRUPT_CPM_RESERVED_08    50
#define CYGNUM_HAL_INTERRUPT_CPM_TIMER4         51
#define CYGNUM_HAL_INTERRUPT_CPM_PC6            52
#define CYGNUM_HAL_INTERRUPT_CPM_SPI            53
#define CYGNUM_HAL_INTERRUPT_CPM_SMC1           54
#define CYGNUM_HAL_INTERRUPT_CPM_SMC2_PIP       55
#define CYGNUM_HAL_INTERRUPT_CPM_PC5            56
#define CYGNUM_HAL_INTERRUPT_CPM_PC4            57
#define CYGNUM_HAL_INTERRUPT_CPM_ERROR          58

#define CYGNUM_HAL_INTERRUPT_CPM_FIRST       CYGNUM_HAL_INTERRUPT_CPM_PC15
#define CYGNUM_HAL_INTERRUPT_CPM_LAST        CYGNUM_HAL_INTERRUPT_CPM_ERROR

#undef  CYGNUM_HAL_ISR_MAX
#define CYGNUM_HAL_ISR_MAX                   CYGNUM_HAL_INTERRUPT_CPM_LAST
#endif

// The vector used by the Real time clock
#define CYGNUM_HAL_INTERRUPT_RTC             CYGNUM_HAL_INTERRUPT_DECREMENTER

//--------------------------------------------------------------------------
// Static data used by HAL

// ISR tables
externC volatile CYG_ADDRESS    hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
externC volatile CYG_ADDRWORD   hal_interrupt_data[CYGNUM_HAL_ISR_COUNT];
externC volatile CYG_ADDRESS    hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT];
// VSR table
externC volatile CYG_ADDRESS    hal_vsr_table[CYGNUM_HAL_VSR_COUNT];

//--------------------------------------------------------------------------
// Default ISR

externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);

//--------------------------------------------------------------------------
// Interrupt state storage

typedef cyg_uint32 CYG_INTERRUPT_STATE;

//--------------------------------------------------------------------------
// Interrupt control macros

#define HAL_DISABLE_INTERRUPTS(_old_)   \
    asm volatile (                      \
        "mfmsr  %0;"                    \
        "lis    4,0;"                   \
        "ori    4,4,0x8000 ;"           \
        "not    5,4;"                   \
        "and    5,%0,5;"                \
        "mtmsr  5;"                     \
        "and    %0,%0,4"                \
        : "=r"(_old_)                   \
        :                               \
        : "r4", "r5"                    \
        );

#define HAL_ENABLE_INTERRUPTS()         \
    asm volatile (                      \
        "mfmsr  3;"                     \
        "lis    4,0;"                   \
        "ori    4,4,0x8000 ;"           \
        "or     3,3,4;"                 \
        "mtmsr  3;"                     \
        :                               \
        :                               \
        : "r3", "r4"                    \
        );

#define HAL_RESTORE_INTERRUPTS(_old_)   \
    asm volatile (                      \
        "mfmsr  3;"                     \
        "lis    4,0;"                   \
        "ori    4,4,0x8000 ;"           \
        "and    4,%0,4;"                \
        "or     4,3,4;"                 \
        "mtmsr  4;"                     \
        :                               \
        : "r"(_old_)                    \
        : "r3", "r4"                    \
        );

// FIXME: using andi with side-effect on cc would be better but causes
// compiler problem.
#define HAL_QUERY_INTERRUPTS(_old_)     \