📄 aeb_misc.c
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//==========================================================================//// aeb_misc.c//// HAL misc board support code for ARM AEB-1////==========================================================================//####COPYRIGHTBEGIN####//// -------------------------------------------// The contents of this file are subject to the Cygnus eCos Public License// Version 1.0 (the "License"); you may not use this file except in// compliance with the License. You may obtain a copy of the License at// http://sourceware.cygnus.com/ecos// // Software distributed under the License is distributed on an "AS IS"// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the// License for the specific language governing rights and limitations under// the License.// // The Original Code is eCos - Embedded Cygnus Operating System, released// September 30, 1998.// // The Initial Developer of the Original Code is Cygnus. Portions created// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved.// -------------------------------------------////####COPYRIGHTEND####//==========================================================================//#####DESCRIPTIONBEGIN####//// Author(s): gthomas// Contributors: gthomas// Date: 1999-02-20// Purpose: HAL board support// Description: Implementations of HAL board interfaces////####DESCRIPTIONEND####////========================================================================*/#include <pkgconf/hal.h>#include <cyg/infra/cyg_type.h> // base types#include <cyg/infra/cyg_trac.h> // tracing macros#include <cyg/infra/cyg_ass.h> // assertion macros#include <cyg/hal/hal_io.h> // IO macros#include <cyg/hal/hal_arch.h> // Register state info#include <cyg/hal/hal_diag.h>#include <cyg/hal/hal_intr.h> // necessary?#include <cyg/hal/hal_cache.h>#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT#include <cyg/hal/drv_api.h> // HAL ISR support#endif/*------------------------------------------------------------------------*/// On-board timer/*------------------------------------------------------------------------*/// Timer registers#define CYG_DEVICE_TIMER0 ((volatile cyg_uint8 *)0xFFFF1800)#define CYG_DEVICE_TIMER1 ((volatile cyg_uint8 *)0xFFFF1804)#define CYG_DEVICE_TIMER2 ((volatile cyg_uint8 *)0xFFFF1808)#define CYG_DEVICE_TIMER_CTL ((volatile cyg_uint8 *)0xFFFF180C)#define CYG_DEVICE_IOCR ((volatile cyg_uint32 *)0xFFFFA410)#define CYG_DEVICE_CPM_PCSR ((volatile cyg_uint32 *)0xFFFFAC04)#define CYG_DEVICE_CPM_CT0CCR ((volatile cyg_uint32 *)0xFFFFAC18)#define CYG_DEVICE_CPM_CT1CCR ((volatile cyg_uint32 *)0xFFFFAC1C)#define CYG_DEVICE_CPM_CT2CCR ((volatile cyg_uint32 *)0xFFFFAC20)#define IOCR_CT0G (0x3<<9)#define IOCR_CT0G_EXTERNAL (0x0<<9)#define IOCR_CT0G_PWM0 (0x1<<9)#define IOCR_CT0G_LOW (0x2<<9)#define IOCR_CT0G_HIGH (0x3<<9)#define IOCR_CT1G (0x3<<11)#define IOCR_CT1G_EXTERNAL (0x0<<11)#define IOCR_CT1G_PWM0 (0x1<<11)#define IOCR_CT1G_LOW (0x2<<11)#define IOCR_CT1G_HIGH (0x3<<11)#define IOCR_CT2G (0x3<<13)#define IOCR_CT2G_EXTERNAL (0x0<<13)#define IOCR_CT2G_PWM0 (0x1<<13)#define IOCR_CT2G_LOW (0x2<<13)#define IOCR_CT2G_HIGH (0x3<<13)#define TIMER_CTL_TYPE (0x1<<0)#define TIMER_CTL_TYPE_BIN (0x0<<0)#define TIMER_CTL_TYPE_BCD (0x1<<0)#define TIMER_CTL_MODE (0x7<<1)#define TIMER_CTL_MODE_IOTC (0x0<<1) // Interrupt on terminal count#define TIMER_CTL_MODE_HROS (0x1<<1) // Hardware retriggerable one-shot#define TIMER_CTL_MODE_RG (0x2<<1) // Rate generator#define TIMER_CTL_MODE_SWG (0x3<<1) // Square-wave generator#define TIMER_CTL_MODE_STS (0x4<<1) // Software triggered strobe#define TIMER_CTL_MODE_HTS (0x5<<1) // Hardware triggered strobe#define TIMER_CTL_RW (0x3<<4)#define TIMER_CTL_RW_LATCH (0x0<<4) // Counter latch#define TIMER_CTL_RW_LSB (0x1<<4)#define TIMER_CTL_RW_MSB (0x2<<4)#define TIMER_CTL_RW_BOTH (0x3<<4)#define TIMER_CTL_SC (0x3<<6)#define TIMER_CTL_SC_CTR0 (0x0<<6)#define TIMER_CTL_SC_CTR1 (0x1<<6)#define TIMER_CTL_SC_CTR2 (0x2<<6)#define TIMER_CTL_SC_RBC (0x3<<6)// Interrupt controller registers#define CYG_DEVICE_ICTL_ICR0 ((volatile cyg_uint32 *)0xFFFFA800)#define CYG_DEVICE_ICTL_ICR1 ((volatile cyg_uint32 *)0xFFFFA804)#define CYG_DEVICE_ICTL_ICLR ((volatile cyg_uint32 *)0xFFFFA808)#define CYG_DEVICE_ICTL_IRQER ((volatile cyg_uint32 *)0xFFFFA80C)#define CYG_DEVICE_ICTL_FIQER ((volatile cyg_uint32 *)0xFFFFA810)#define CYG_DEVICE_ICTL_IRQSR ((volatile cyg_uint32 *)0xFFFFA814)#define CYG_DEVICE_ICTL_FIQSR ((volatile cyg_uint32 *)0xFFFFA818)#define CYG_DEVICE_ICTL_IPR ((volatile cyg_uint32 *)0xFFFFA81C)#define ICTL_ICR0_CH0 (0x3<<0)#define ICTL_ICR0_CH0_HL (0x1<<0)#define ICTL_ICR0_CH0_HL_AL (0x0<<0) // Active low#define ICTL_ICR0_CH0_HL_AH (0x1<<0) // Active high#define ICTL_ICR0_CH0_EL (0x2<<0)#define ICTL_ICR0_CH0_EL_LT (0x0<<0) // Level triggered#define ICTL_ICR0_CH0_EL_ET (0x2<<0) // Edge triggered#define ICTL_ICR0_CH1 (0x3<<2)#define ICTL_ICR0_CH1_HL (0x1<<2)#define ICTL_ICR0_CH1_HL_AL (0x0<<2) // Active low#define ICTL_ICR0_CH1_HL_AH (0x1<<2) // Active high#define ICTL_ICR0_CH1_EL (0x2<<2)#define ICTL_ICR0_CH1_EL_LT (0x0<<2) // Level triggered#define ICTL_ICR0_CH1_EL_ET (0x2<<2) // Edge triggered#define ICTL_ICR0_CH2 (0x3<<4)#define ICTL_ICR0_CH2_HL (0x1<<4)#define ICTL_ICR0_CH2_HL_AL (0x0<<4) // Active low#define ICTL_ICR0_CH2_HL_AH (0x1<<4) // Active high#define ICTL_ICR0_CH2_EL (0x2<<4)#define ICTL_ICR0_CH2_EL_LT (0x0<<4) // Level triggered#define ICTL_ICR0_CH2_EL_ET (0x2<<4) // Edge triggered#define ICTL_ICR0_CH3 (0x3<<6)#define ICTL_ICR0_CH3_HL (0x1<<6)#define ICTL_ICR0_CH3_HL_AL (0x0<<6) // Active low#define ICTL_ICR0_CH3_HL_AH (0x1<<6) // Active high#define ICTL_ICR0_CH3_EL (0x2<<6)#define ICTL_ICR0_CH3_EL_LT (0x0<<6) // Level triggered#define ICTL_ICR0_CH3_EL_ET (0x2<<6) // Edge triggered#define ICTL_ICR0_CH4 (0x3<<8)#define ICTL_ICR0_CH4_HL (0x1<<8)#define ICTL_ICR0_CH4_HL_AL (0x0<<8) // Active low#define ICTL_ICR0_CH4_HL_AH (0x1<<8) // Active high#define ICTL_ICR0_CH4_EL (0x2<<8)#define ICTL_ICR0_CH4_EL_LT (0x0<<8) // Level triggered#define ICTL_ICR0_CH4_EL_ET (0x2<<8) // Edge triggered#define ICTL_ICR0_CH5 (0x3<<10)#define ICTL_ICR0_CH5_HL (0x1<<10)#define ICTL_ICR0_CH5_HL_AL (0x0<<10) // Active low#define ICTL_ICR0_CH5_HL_AH (0x1<<10) // Active high#define ICTL_ICR0_CH5_EL (0x2<<10)#define ICTL_ICR0_CH5_EL_LT (0x0<<10) // Level triggered#define ICTL_ICR0_CH5_EL_ET (0x2<<10) // Edge triggered#define ICTL_ICR1_CH6 (0x1<<0)#define ICTL_ICR1_CH6_HL (0x1<<0)#define ICTL_ICR1_CH6_HL_AL (0x0<<0) // Active low#define ICTL_ICR1_CH6_HL_AH (0x1<<0) // Active high#define ICTL_ICR1_CH7 (0x1<<1)#define ICTL_ICR1_CH7_HL (0x1<<1)#define ICTL_ICR1_CH7_HL_AL (0x0<<1) // Active low#define ICTL_ICR1_CH7_HL_AH (0x1<<1) // Active high#define ICTL_ICR1_CH8 (0x1<<2)#define ICTL_ICR1_CH8_HL (0x1<<2)#define ICTL_ICR1_CH8_HL_AL (0x0<<2) // Active low#define ICTL_ICR1_CH8_HL_AH (0x1<<2) // Active high// Clock control registers#define PCSR_CT0CS (1<<3)#define PCSR_CT1CS (1<<4)#define PCSR_CT2CS (1<<5)#define CT_X16 16#undef _TIMERS_TESTING#ifdef _TIMERS_TESTINGstatic void aeb_setup_timer1(cyg_uint32 period);#endifstatic cyg_uint32 _period;#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORTstatic cyg_interrupt abort_interrupt;static cyg_handle_t abort_interrupt_handle;// This ISR is called only for the Abort button interruptstatic intaeb_abort_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs){ cyg_hal_gdb_interrupt (regs->pc); cyg_drv_interrupt_acknowledge(CYGNUM_HAL_INTERRUPT_EXT0); return 0; // No need to run DSR}#endifvoid hal_clock_initialize(cyg_uint32 period){ cyg_uint32 iocr; // Set counter GATE input low (0) to halt counter while it's being setup⌨️ 快捷键说明
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