hal_intr.h

ecos为实时嵌入式操作系统

#define HAL_TRANSLATE_VECTOR(_vector_,_index_)                             \
              _index_ = (((_vector_)<=CYGNUM_HAL_INTERRUPT_SYSTEM_ERROR) ? \
                         (_vector_) :                                      \
                         (((_vector_)>>2)+CYGNUM_HAL_INTERRUPT_RESERVED_3))

#endif

#endif


//--------------------------------------------------------------------------
// Interrupt and VSR attachment macros

#define HAL_INTERRUPT_IN_USE( _vector_, _state_)                          \
    CYG_MACRO_START                                                       \
    cyg_uint32 _index_;                                                   \
    HAL_TRANSLATE_VECTOR ((_vector_), _index_);                           \
                                                                          \
    if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)NULL )            \
        (_state_) = 0;                                                    \
    else                                                                  \
        (_state_) = 1;                                                    \
    CYG_MACRO_END

#define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ )       \
{                                                                       \
    cyg_uint32 _index_;                                                 \
    HAL_TRANSLATE_VECTOR(_vector_,_index_);                             \
                                                                        \
    if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)NULL )          \
    {                                                                   \
        hal_interrupt_handlers[_index_] = (CYG_ADDRESS)_isr_;           \
        hal_interrupt_data[_index_] = (CYG_ADDRWORD)_data_;             \
        hal_interrupt_objects[_index_] = (CYG_ADDRESS)_object_;         \
    }                                                                   \
}

#define HAL_INTERRUPT_DETACH( _vector_, _isr_ )                         \
{                                                                       \
    cyg_uint32 _index_;                                                 \
    HAL_TRANSLATE_VECTOR(_vector_,_index_);                             \
                                                                        \
    if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)_isr_ )         \
    {                                                                   \
        hal_interrupt_handlers[_index_] = (CYG_ADDRESS)NULL;            \
        hal_interrupt_data[_index_] = 0;                                \
        hal_interrupt_objects[_index_] = 0;                             \
    }                                                                   \
}

#define HAL_VSR_GET( _vector_, _pvsr_ )                                 \
    *((CYG_ADDRESS *)_pvsr_) = hal_vsr_table[_vector_];
    

#define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ )                       \
    if( _poldvsr_ != NULL )                                             \
        *(CYG_ADDRESS *)_poldvsr_ = hal_vsr_table[_vector_];            \
    hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_;


//--------------------------------------------------------------------------
// Interrupt controller access
// Read interrupt control registers back after writing to them. This
// ensures that the written value is not sitting in the store buffers
// when interrupts are re-enabled.
#define HAL_INTERRUPT_MASK( _vector_ )                                  \
{                                                                       \
    /* ICRs are 16 bit regs at 32 bit spacing */                        \
    cyg_ucount16 _index_ = ((_vector_)>>2)<<1;                          \
                                                                        \
    /* read the appropriate interrupt control register */               \
    cyg_uint16 _icr_ = mn10300_interrupt_control[_index_];              \
                                                                        \
    /* clear interrupt enable bit for this vector */                    \
    _icr_ &= ~(0x0100<<((_vector_)&3));                                 \
                                                                        \
    /* restore the interrupt control register */                        \
    mn10300_interrupt_control[_index_] = _icr_;                         \
    _icr_ = mn10300_interrupt_control[_index_];                         \
}

#define HAL_INTERRUPT_UNMASK( _vector_ )                                \
{                                                                       \
    /* ICRs are 16 bit regs at 32 bit spacing */                        \
    cyg_ucount16 _index_ = (_vector_>>2)<<1;                            \
                                                                        \
    /* read the appropriate interrupt control register */               \
    cyg_uint16 _icr_ = mn10300_interrupt_control[_index_];              \
                                                                        \
    /* set interrupt enable bit for this vector */                      \
    _icr_ |= (0x0100<<(_vector_&3));                                    \
                                                                        \
    /* restore the interrupt control register */                        \
    mn10300_interrupt_control[_index_] = _icr_;                         \
    _icr_ = mn10300_interrupt_control[_index_];                         \
}

#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ )                   \
{                                                               \
    /* ICRs are 16 bit regs at 32 bit spacing */                \
    cyg_ucount16 _index_ = ((_vector_)>>2)<<1;                  \
                                                                \
    /* read the appropriate interrupt control register */       \
    cyg_uint16 _icr_ = mn10300_interrupt_control[_index_];      \
                                                                \
    /* clear interrupt request bit for this vector */           \
    _icr_ &= ~(0x0010<<((_vector_)&3));                         \
                                                                \
    /* set interrupt detect bit for this vector */              \
    _icr_ |= (0x0001<<((_vector_)&3));                          \
                                                                \
    /* restore the interrupt control register */                \
    mn10300_interrupt_control[_index_] = _icr_;                 \
    _icr_ = mn10300_interrupt_control[_index_];                 \
}

#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ )      \
{                                                               \
    cyg_uint32 _v_ = _vector_;                                  \
    cyg_uint16 _val_ = 0;                                       \
    cyg_uint16 _reg_;                                           \
                                                                \
    /* adjust vector to bit offset in EXTMD */                  \
    _v_ -= CYGNUM_HAL_INTERRUPT_EXTERNAL_0;                     \
    _v_ >>= 1;                                                  \
                                                                \
    /* set bits according to requirements */                    \
    if( _up_ ) _val_ |= 1;                                      \
    if( !(_level_) ) _val_ |= 2;                                \
                                                                \
    /* get EXTMD */                                             \
    _reg_ = mn10300_interrupt_control[0x180>>1];                \
                                                                \
    /* clear old value and set new */                           \
    _reg_ &= ~(3<<_v_);                                         \
    _reg_ |= _val_<<_v_;                                        \
                                                                \
    /* restore EXTMD */                                         \
    mn10300_interrupt_control[0x180>>1] = _reg_;                \
}

#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ )            \
{                                                               \
    /* ICRs are 16 bit regs at 32 bit spacing */                \
    cyg_ucount16 _index_ = (_vector_>>2)<<1;                    \
                                                                \
    /* read the appropriate interrupt control register */       \
    cyg_uint16 _icr_ = mn10300_interrupt_control[_index_];      \
                                                                \
    /* set interrupt level for this group of vectors */         \
    _icr_ &= 0x0FFF;                                            \
    _icr_ |= (_level_)<<12;                                     \
                                                                \
    /* restore the interrupt control register */                \
    mn10300_interrupt_control[_index_] = _icr_;                 \
    _icr_ = mn10300_interrupt_control[_index_];                 \
}

//--------------------------------------------------------------------------
// Clock control


#if 0 // defined(CYG_HAL_MN10300_SIM)

#define OEA_DEV                 0x31000000

#define HAL_SWAP(x) ((((x)&0xff)<<24)|(((x)&0xff00)<<8)|        \
                (((x)&0xff0000)>>8)|(((x)&0xff000000)>>24))

#define PAL_COUNTDOWN_TIMER     0x20  // one shot on IR0
#define PAL_COUNTDOWN_VALUE     0x24
#define PAL_PERIODIC_TIMER      0x28  // repeating on IR1
#define PAL_PERIODIC_VALUE      0x2c


// IRQ1 set to receive clock intrs
#define HAL_CLOCK_INITIALIZE( _period_ )                        \
{                                                               \
    volatile cyg_uint32 *timer = (cyg_uint32 *)                 \
        (OEA_DEV + PAL_PERIODIC_TIMER);                         \
    cyg_uint32 p = _period_;                                    \
                                                                \
    *timer = HAL_SWAP(p);                                       \
}

#elif defined(CYG_HAL_MN10300_MN103000)

#define HAL_CLOCK_INITIALIZE( _period_ )                        \
{                                                               \
    volatile cyg_uint16 *timer_ctr = (cyg_uint16 *)TIMER_BR;    \
    volatile cyg_uint16 *timer_mode = (cyg_uint16 *)TIMER_MD;   \
    volatile cyg_uint8 *timer_a_mode = (cyg_uint8 *)0x34001084; \
                                                                \
    *timer_a_mode = 0x04;                                       \
                                                                \
    *timer_ctr = 0xf000;                                        \
                                                                \
    *timer_mode = 0x0013;                                       \
    *timer_mode = 0x4013;                                       \
    *timer_mode = 0x0013;                                       \
    *timer_mode = 0x8013;                                       \
}

#elif defined(CYG_HAL_MN10300_MN103002)

#define HAL_CLOCK_INITIALIZE( _period_ )                                \
{                                                                       \
    volatile cyg_uint16 *timer4_br      = (cyg_uint16 *)TIMER4_BR;      \
    volatile cyg_uint8 *timer4_md       = (cyg_uint8 *)TIMER4_MD;       \
    volatile cyg_uint16 *timer5_br      = (cyg_uint16 *)TIMER5_BR;      \
    volatile cyg_uint8 *timer5_md       = (cyg_uint8 *)TIMER5_MD;       \
                                                                        \
    /* Set timers 4 and 5 into cascade mode */                          \
                                                                        \
    *timer5_br = (_period_)>>16;                                        \
                                                                        \
    *timer5_md = 0x40;                                                  \
    *timer5_md = 0x83;                                                  \
                                                                        \
    *timer4_br = (_period_)&0x0000FFFF;                                 \
                                                                        \
    *timer4_md = 0x40;                                                  \
    *timer4_md = 0x80;                                                  \
}

#else

#error Undefined MN10300 model

#endif    

#define HAL_CLOCK_RESET( _vector_, _period_ )

#if 0 //def CYG_HAL_MN10300_SIM

// This timer counts down, so subtract from set value.
#define HAL_CLOCK_READ( _pvalue_ )                                      \
{                                                                       \
    volatile cyg_uint32 *timer = (cyg_uint32 *)                         \
        (OEA_DEV + PAL_PERIODIC_TIMER);                                 \
    volatile cyg_uint32 *value = (cyg_uint32 *)                         \
        (OEA_DEV + PAL_PERIODIC_VALUE);                                 \
    cyg_uint32 t,v;                                                     \
    t = *timer;                                                         \
    v = *value;                                                         \
    *(_pvalue_) = HAL_SWAP(t) - HAL_SWAP(v);                            \
}

#else // CYG_HAL_MN10300_SIM not
#define HAL_CLOCK_READ( _pvalue_ )                                      \
{                                                                       \
    volatile cyg_uint16 *timer4_cr = (cyg_uint16 *)TIMER4_CR;           \
    volatile cyg_uint16 *timer5_cr = (cyg_uint16 *)TIMER5_CR;           \
                                                                        \
    cyg_uint16 t5;                                                      \
    cyg_uint16 t4;                                                      \
                                                                        \
    /* Loop reading the two timers until we can read t5 twice   */      \
    /* with the same value. This avoids getting silly times if  */      \
    /* the timers carry between reading the two regs.           */      \
    do {                                                                \
        t5 = *timer5_cr;                                                \
        t4 = *timer4_cr;                                                \
    } while( t5 != *timer5_cr );                                        \
                                                                        \
    *(_pvalue_) = CYGNUM_KERNEL_COUNTERS_RTC_PERIOD - ((t5<<16) + t4);  \
}

// FIXME: above line should not use CYGNUM_KERNEL_COUNTERS_RTC_PERIOD since
// this means the HAL gets configured by kernel options even when the
// kernel is disabled!

#endif // CYG_HAL_MN10300_SIM

#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
#define HAL_CLOCK_LATENCY(_pvalue_) HAL_CLOCK_READ(_pvalue_)
#endif

//--------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_HAL_INTR_H
// EOF hal_intr.h