hal_intr.h

ecos为实时嵌入式操作系统

#define CYGNUM_HAL_INTERRUPT_RESERVED_29          29
#define CYGNUM_HAL_INTERRUPT_RESERVED_30          30
#define CYGNUM_HAL_INTERRUPT_RESERVED_31          31

#define CYGNUM_HAL_INTERRUPT_TIMER_6              32
#define CYGNUM_HAL_INTERRUPT_RESERVED_33          33
#define CYGNUM_HAL_INTERRUPT_RESERVED_34          34
#define CYGNUM_HAL_INTERRUPT_RESERVED_35          35

#define CYGNUM_HAL_INTERRUPT_TIMER_6_COMPARE_A    36
#define CYGNUM_HAL_INTERRUPT_RESERVED_37          37
#define CYGNUM_HAL_INTERRUPT_RESERVED_38          38
#define CYGNUM_HAL_INTERRUPT_RESERVED_39          39

#define CYGNUM_HAL_INTERRUPT_TIMER_6_COMPARE_B    40
#define CYGNUM_HAL_INTERRUPT_RESERVED_41          41
#define CYGNUM_HAL_INTERRUPT_RESERVED_42          42
#define CYGNUM_HAL_INTERRUPT_RESERVED_43          43

#define CYGNUM_HAL_INTERRUPT_RESERVED_44          44
#define CYGNUM_HAL_INTERRUPT_RESERVED_45          45
#define CYGNUM_HAL_INTERRUPT_RESERVED_46          46
#define CYGNUM_HAL_INTERRUPT_RESERVED_47          47

#define CYGNUM_HAL_INTERRUPT_DMA0                 48
#define CYGNUM_HAL_INTERRUPT_RESERVED_49          49
#define CYGNUM_HAL_INTERRUPT_RESERVED_50          50
#define CYGNUM_HAL_INTERRUPT_RESERVED_51          51

#define CYGNUM_HAL_INTERRUPT_DMA1                 52
#define CYGNUM_HAL_INTERRUPT_RESERVED_53          53
#define CYGNUM_HAL_INTERRUPT_RESERVED_54          54
#define CYGNUM_HAL_INTERRUPT_RESERVED_55          55

#define CYGNUM_HAL_INTERRUPT_DMA2                 56
#define CYGNUM_HAL_INTERRUPT_RESERVED_57          57
#define CYGNUM_HAL_INTERRUPT_RESERVED_58          58
#define CYGNUM_HAL_INTERRUPT_RESERVED_59          59

#define CYGNUM_HAL_INTERRUPT_DMA3                 60
#define CYGNUM_HAL_INTERRUPT_RESERVED_61          61
#define CYGNUM_HAL_INTERRUPT_RESERVED_62          62
#define CYGNUM_HAL_INTERRUPT_RESERVED_63          63

#define CYGNUM_HAL_INTERRUPT_SERIAL_0_RX          64
#define CYGNUM_HAL_INTERRUPT_RESERVED_65          65
#define CYGNUM_HAL_INTERRUPT_RESERVED_66          66
#define CYGNUM_HAL_INTERRUPT_RESERVED_67          67

#define CYGNUM_HAL_INTERRUPT_SERIAL_0_TX          68
#define CYGNUM_HAL_INTERRUPT_RESERVED_69          69
#define CYGNUM_HAL_INTERRUPT_RESERVED_70          70
#define CYGNUM_HAL_INTERRUPT_RESERVED_71          71

#define CYGNUM_HAL_INTERRUPT_SERIAL_1_RX          72
#define CYGNUM_HAL_INTERRUPT_RESERVED_73          73
#define CYGNUM_HAL_INTERRUPT_RESERVED_74          74
#define CYGNUM_HAL_INTERRUPT_RESERVED_75          75

#define CYGNUM_HAL_INTERRUPT_SERIAL_1_TX          76
#define CYGNUM_HAL_INTERRUPT_RESERVED_77          77
#define CYGNUM_HAL_INTERRUPT_RESERVED_78          78
#define CYGNUM_HAL_INTERRUPT_RESERVED_79          79

#define CYGNUM_HAL_INTERRUPT_SERIAL_2_RX          80
#define CYGNUM_HAL_INTERRUPT_RESERVED_81          81
#define CYGNUM_HAL_INTERRUPT_RESERVED_82          82
#define CYGNUM_HAL_INTERRUPT_RESERVED_83          83

#define CYGNUM_HAL_INTERRUPT_SERIAL_2_TX          84
#define CYGNUM_HAL_INTERRUPT_RESERVED_85          85
#define CYGNUM_HAL_INTERRUPT_RESERVED_86          86
#define CYGNUM_HAL_INTERRUPT_RESERVED_87          87

#define CYGNUM_HAL_INTERRUPT_RESERVED_88          88
#define CYGNUM_HAL_INTERRUPT_RESERVED_89          89
#define CYGNUM_HAL_INTERRUPT_RESERVED_90          90
#define CYGNUM_HAL_INTERRUPT_RESERVED_91          91

#define CYGNUM_HAL_INTERRUPT_EXTERNAL_0           92
#define CYGNUM_HAL_INTERRUPT_RESERVED_93          93
#define CYGNUM_HAL_INTERRUPT_RESERVED_94          94
#define CYGNUM_HAL_INTERRUPT_RESERVED_95          95

#define CYGNUM_HAL_INTERRUPT_EXTERNAL_1           96
#define CYGNUM_HAL_INTERRUPT_RESERVED_97          97
#define CYGNUM_HAL_INTERRUPT_RESERVED_98          98
#define CYGNUM_HAL_INTERRUPT_RESERVED_99          99

#define CYGNUM_HAL_INTERRUPT_EXTERNAL_2           100
#define CYGNUM_HAL_INTERRUPT_RESERVED_101         101
#define CYGNUM_HAL_INTERRUPT_RESERVED_102         102
#define CYGNUM_HAL_INTERRUPT_RESERVED_103         103

#define CYGNUM_HAL_INTERRUPT_EXTERNAL_3           104
#define CYGNUM_HAL_INTERRUPT_RESERVED_105         105
#define CYGNUM_HAL_INTERRUPT_RESERVED_106         106
#define CYGNUM_HAL_INTERRUPT_RESERVED_107         107

#define CYGNUM_HAL_INTERRUPT_EXTERNAL_4           108
#define CYGNUM_HAL_INTERRUPT_RESERVED_109         109
#define CYGNUM_HAL_INTERRUPT_RESERVED_110         110
#define CYGNUM_HAL_INTERRUPT_RESERVED_111         111

#define CYGNUM_HAL_INTERRUPT_EXTERNAL_5           112
#define CYGNUM_HAL_INTERRUPT_RESERVED_113         113
#define CYGNUM_HAL_INTERRUPT_RESERVED_114         114
#define CYGNUM_HAL_INTERRUPT_RESERVED_115         115

#define CYGNUM_HAL_INTERRUPT_EXTERNAL_6           116
#define CYGNUM_HAL_INTERRUPT_RESERVED_117         117
#define CYGNUM_HAL_INTERRUPT_RESERVED_118         118
#define CYGNUM_HAL_INTERRUPT_RESERVED_119         119

#define CYGNUM_HAL_INTERRUPT_EXTERNAL_7           120
#define CYGNUM_HAL_INTERRUPT_RESERVED_121         121
#define CYGNUM_HAL_INTERRUPT_RESERVED_122         122
#define CYGNUM_HAL_INTERRUPT_RESERVED_123         123

#define CYGNUM_HAL_ISR_MIN                     0
#define CYGNUM_HAL_ISR_MAX                     123

#define CYGNUM_HAL_ISR_COUNT                   (3+((CYGNUM_HAL_ISR_MAX+1)/4))

#endif

// The vector used by the Real time clock

#ifdef CYG_HAL_MN10300_SIM
#  define CYGNUM_HAL_INTERRUPT_RTC           CYGNUM_HAL_INTERRUPT_TIMER_5
//# define CYGNUM_HAL_INTERRUPT_RTC          CYGNUM_HAL_INTERRUPT_EXTERNAL_1
#else
# ifdef CYG_HAL_MN10300_MN103000
#  define CYGNUM_HAL_INTERRUPT_RTC           CYGNUM_HAL_INTERRUPT_TIMER_8
# endif
# ifdef CYG_HAL_MN10300_MN103002
#  define CYGNUM_HAL_INTERRUPT_RTC           CYGNUM_HAL_INTERRUPT_TIMER_5
# endif
#endif

//--------------------------------------------------------------------------
// Timer control registers.

// On simulator we use simulated external interrupt

#if defined(CYG_HAL_MN10300_MN103002)

// On the mn103002 we use timers 4 and 5

#define TIMER4_CR        0x340010a0
#define TIMER4_BR        0x34001090
#define TIMER4_MD        0x34001080

#define TIMER5_CR        0x340010a2
#define TIMER5_BR        0x34001092
#define TIMER5_MD        0x34001082

#define TIMER_CR        TIMER5_CR
#define TIMER_BR        TIMER5_BR
#define TIMER_MD        TIMER5_MD

#define TIMER0_MD       0x34001000
#define TIMER0_BR       0x34001010
#define TIMER0_CR       0x34001020

#elif defined(CYG_HAL_MN10300_MN103000)

// on the mn103000 we use timers 4 and 5
#define TIMER4_CR        0x340010a0
#define TIMER4_BR        0x34001090
#define TIMER4_MD        0x34001080

#define TIMER5_CR        0x340010a2
#define TIMER5_BR        0x34001092
#define TIMER5_MD        0x34001082

#define TIMER_CR        TIMER5_CR
#define TIMER_BR        TIMER5_BR
#define TIMER_MD        TIMER5_MD

#define TIMER0_MD       0x34001000
#define TIMER0_BR       0x34001010
#define TIMER0_CR       0x34001020

#endif

//--------------------------------------------------------------------------
// Static data used by HAL

// ISR tables
externC volatile CYG_ADDRESS    hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
externC volatile CYG_ADDRWORD   hal_interrupt_data[CYGNUM_HAL_ISR_COUNT];
externC volatile CYG_ADDRESS    hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT];

// VSR table
externC volatile CYG_ADDRESS    hal_vsr_table[CYGNUM_HAL_VSR_COUNT];

// MN10300 interrupt control registers, mapped by linker script.
externC volatile cyg_uint16     mn10300_interrupt_control[0x300/2];

//--------------------------------------------------------------------------
// Interrupt state storage

typedef cyg_uint32 CYG_INTERRUPT_STATE;

//--------------------------------------------------------------------------
// Interrupt control macros

#define HAL_DISABLE_INTERRUPTS(_old_)   \
        asm volatile (                  \
            "mov        psw,%0;"        \
            "mov        0xF7FF,d0;"     \
            "and        %0,d0;"         \
            "mov        d0,psw;"        \
            "and        0x0800,%0;"     \
            : "=d"(_old_)               \
            :                           \
            : "d0"                      \
            );

#define HAL_ENABLE_INTERRUPTS()         \
        asm volatile (                  \
            "mov        psw,d0;"        \
            "or         0x0800,d0;"     \
            "mov        d0,psw;"        \
            :                           \
            :                           \
            : "d0"                      \
            );

#define HAL_RESTORE_INTERRUPTS(_old_)   \
        asm volatile (                  \
            "mov        psw,d1;"        \
            "or         %0,d1;"         \
            "mov        d1,psw;"        \
            :                           \
            : "d"(_old_)                \
            : "d1"                      \
            );

#define HAL_QUERY_INTERRUPTS(_old_)     \
        asm volatile (                  \
            "mov        psw,%0;"        \
            "and        0x0800,%0;"     \
            : "=d"(_old_)               \
            );

//--------------------------------------------------------------------------
// Translate a vector number into an ISR table index.
// If we have chained interrupts we have just a single ISR per priority
// level. On the MN103000 there are several interrupts per controller,
// so we have to decode to one of 100 vectors. On the MN103002 there is
// only one interrupt per controller, so we can have just one ISR per
// controller, except for the NMI vectors which occupy the first 3 slots.

#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN

#define HAL_TRANSLATE_VECTOR(_vector_,_index_)                             \
{                                                                          \
    if( _vector_ <= CYGNUM_HAL_INTERRUPT_SYSTEM_ERROR )                    \
        (_index_) = (_vector_);                                            \
    else                                                                   \
    {                                                                      \
        /* ICRs are 16 bit regs at 32 bit spacing */                       \
        cyg_ucount16 _ix_ = ((_vector_)>>2)<<1;                            \
                                                                           \
        /* read the appropriate interrupt control register */              \
        cyg_uint16 _icr_ = mn10300_interrupt_control[_ix_];                \
                                                                           \
        /* extract interrupt priority level */                             \
        _index_ = CYGNUM_HAL_INTERRUPT_RESERVED_3 + ((_icr_ >> 12) & 0x7); \
    }                                                                      \
}

#else

#if defined(CYG_HAL_MN10300_MN103000)

#define HAL_TRANSLATE_VECTOR(_vector_,_index_) _index_ = (_vector_)

#elif defined(CYG_HAL_MN10300_MN103002)