vectors.s

ecos为实时嵌入式操作系统

##=============================================================================
##
##	vectors.S
##
##	MIPS exception vectors
##
##=============================================================================
#####COPYRIGHTBEGIN####
#
# -------------------------------------------
# The contents of this file are subject to the Cygnus eCos Public License
# Version 1.0 (the "License"); you may not use this file except in
# compliance with the License.  You may obtain a copy of the License at
# http://sourceware.cygnus.com/ecos
# 
# Software distributed under the License is distributed on an "AS IS"
# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the
# License for the specific language governing rights and limitations under
# the License.
# 
# The Original Code is eCos - Embedded Cygnus Operating System, released
# September 30, 1998.
# 
# The Initial Developer of the Original Code is Cygnus.  Portions created
# by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions.  All Rights Reserved.
# -------------------------------------------
#
#####COPYRIGHTEND####
##=============================================================================
#######DESCRIPTIONBEGIN####
##
## Author(s): 	nickg
## Contributors:	nickg
## Date:	1998-02-04
## Purpose:	MIPS exception vectors
## Description:	This file defines the code placed into the exception
##              vectors. It also contains the first level default VSRs
##		that save and restore state for both exceptions and
##		interrupts.
##
######DESCRIPTIONEND####
##
##=============================================================================

#	.file	"vectors.S"

#include <pkgconf/system.h>	
#include <pkgconf/hal.h>

#ifdef CYGPKG_KERNEL
# include <pkgconf/kernel.h>	
#endif
			
#include <cyg/hal/mips.inc>
		
	.extern cyg_instrument

##-----------------------------------------------------------------------------

#define MAX_SAVE_REG	31	
			
#if defined(CYG_HAL_STARTUP_RAM)
# if defined(CYG_HAL_MIPS_SIM) || !defined(CYG_HAL_USE_ROM_MONITOR)
#  define INITIAL_SR	0x1000ff00	/* CP0 usable, Ints enabled	*/
//#define INITIAL_SR	0x10000000	/* CP0 usable, Ints disabled	*/
# else
#  define INITIAL_SR	0x1040ff00	/* as above + ROM vectors used	*/
# endif	
#elif defined(CYG_HAL_STARTUP_ROM)
# define INITIAL_SR	0x1040ff00	/* as above + ROM vectors used	*/
#endif

## ROM timing characteristics dependent on the clock speed.
		
#if (CYGHWR_HAL_MIPS_CPU_FREQ == 50)
#define ROM_CCR0_INIT	0x00000420
#define DRAM_DREFC_INIT	0x00000180
#elif (CYGHWR_HAL_MIPS_CPU_FREQ == 66)
#define ROM_CCR0_INIT	0x00000520
#define DRAM_DREFC_INIT	0x00000200
#else
#error Unsupported clock frequency		
#endif

## DRAM configuration dependent on the DRAM device used.
      ## for 16MByte (4MBit (x4bit) x 8)           0x08024030
      ## for 4MByte (1MBit (x4bit) x 8)            0x08013020
      ## for 8MByte (1MBit (x4bit) x 8 x 2 banks)  0x08013020

#if defined CYGHWR_HAL_TX39_JMR3904_DRAM_CONFIG_INIT
#define DRAM_CONFIG_INIT CYGHWR_HAL_TX39_JMR3904_DRAM_CONFIG_INIT
#else
#define DRAM_CONFIG_INIT 0x08024030
#endif

##-----------------------------------------------------------------------------
## Hardware supplied vectors
	
	.set	noreorder
	.set	noat
 
	.section ".reset_vector","ax"

	# Reset vector at 0xBFC00000
	
	.globl	reset_vector
reset_vector:
	la	v0,_start		# jump to start
	jr	v0
	nop				# (delay slot)

	.section ".debug_vector","ax"
		
	# Debug vector at 0xBFC00200
	
	.globl	debug_vector
debug_vector:
	la	k0,32
	la	k1,hal_vsr_table	# Get VSR table
	lw	k1,32*4(k1)		# load debug vector
	jr	k1			# go there
	nop				# (delay slot)

	.section ".other_vector","ax"

	# Common vector at 0x80000080 or 0xBFC00180
	
	.globl	other_vector	
other_vector:
	mfc0	k0,cause		# K0 = exception cause
	nop
	andi	k0,k0,0x7F		# isolate exception code
	la	k1,hal_vsr_table	# address of VSR table
	add	k1,k1,k0		# offset of VSR entry
	lw	k1,0(k1)		# k1 = pointer to VSR
	jr	k1			# go there
	nop				# (delay slot)
		
	.section ".utlb_vector","ax"

	.globl	utlb_vector
utlb_vector:	
	la	k0,33
	la	k1,hal_vsr_table	# Get VSR table
	lw	k1,33*4(k1)		# load utlb vector
	jr	k1			# go there
	nop				# (delay slot)

	
##-----------------------------------------------------------------------------
## Startup code
	
	.text
	
	.globl	_start
	.ent	_start
_start:
	# init CPU registers
	mtc0	zero,cause		# zero cause reg
	la	v0,INITIAL_SR
	mtc0	v0,sr
	mfc0	v0,config
	nop
	.set	at
	and	v0,v0,0xffffffcf
#	la	v0,0
	.set	noat
	mtc0	v0,config

	
	# Initialize hardware

#ifdef CYG_HAL_MIPS_JMR3904
	
	# These mappings need to be set up before we
	# can use the stack and make calls to other
	# functions

	# If we have been started from Cygmon, it should have
	# already done a lot of this, but it should do no harm
	# to reinitialize the following registers.
			
	# SCS0,1 base addr of ISA & PCI
	la	a0,0xffffe010
	la	a1,0x20201410
	sw	a1,0(a0)	

	la	a0,0xffffe014
	la	a1,0xfffffcfc
	sw	a1,0(a0)	

	# ROM configuration
	.set	at
	la	a0,0xffff9000
	lw	a1,0(a0)
	and	a1,a1,0xffff0004	# keep hardware defaults
	or	a1,ROM_CCR0_INIT	# install our values
	sw	a1,0(a0)	
	.set	noat

	# SRAM config
	la	a0,0xffff9100
	la	a1,0x00000000
	sw	a1,0(a0)	

	# ISA bus setup
	la	a0,0xb2100000
	la	a1,4
	sb	a1,0(a0)	
	
	# Clear IMR (to cope with JMON)
	la	a0,0xffffc004
	la	a1,0x00000000
	sw	a1,0(a0)

#if defined(CYG_HAL_STARTUP_ROM)

	# Only do this in ROM configurations.
	
	# DRAM Configuration
	la	a0, 0xffff8000
	la	a1, DRAM_CONFIG_INIT
	sw	a1, 0(a0)
	
	# DBMR0
	la	a0, 0xffff8004
	la	a1, 0x00000000	
	sw	a1, 0(a0)
	
	# DWR0
	la	a0, 0xffff8008
	la	a1, 0x00000000
	sw	a1, 0(a0)
	
        # DREFC - Depends on clock requency
	la	a0, 0xffff8800
	la	a1, DRAM_DREFC_INIT
	sw	a1, 0(a0)

#endif

	# Set up PIO0 for output
	la	a0,0xfffff500
	la	a1,0xff
	sb	a1,0(a0)
	la	a1,0
	sb	a1,4(a0)	
				
#endif	
	
	# Load Global Pointer register.
	la	gp,_gp

	# load initial stack pointer
	la	a0,__interrupt_stack
	move	sp,a0

#if defined(CYG_HAL_STARTUP_ROM) || \
    (defined(CYG_HAL_STARTUP_RAM) && !defined(CYG_HAL_USE_ROM_MONITOR))
	
	# If we are starting up from ROM, or we are starting in
	# RAM and NOT using a ROM monitor, initialize the VSR table.

	la	a0,__default_interrupt_vsr
	la	a1,__default_exception_vsr
	la	a3,hal_vsr_table
	sw	a0,0(a3)
	sw	a1,1*4(a3)
	sw	a1,2*4(a3)
	sw	a1,3*4(a3)
	sw	a1,4*4(a3)
	sw	a1,5*4(a3)
	sw	a1,6*4(a3)
	sw	a1,7*4(a3)
	sw	a1,8*4(a3)
	sw	a1,9*4(a3)
	sw	a1,10*4(a3)
	sw	a1,11*4(a3)
	sw	a1,12*4(a3)
	sw	a1,13*4(a3)
	sw	a1,14*4(a3)
	sw	a1,15*4(a3)

	sw	a1,32*4(a3)
	sw	a1,33*4(a3)
	
#ifdef CYG_HAL_ROM_MONITOR

	# Install vectors to debug read and write functions
	
	.extern	hal_diag_write_char
	.extern	hal_diag_read_char
	.extern	breakpoint	

	la	a0,hal_diag_write_char
	sw	a0,63*4(a3)
	la	a1,hal_diag_read_char
	sw	a1,62*4(a3)
	la	a0,breakpoint
	sw	a0,61*4(a3)	
	
#endif		
		
#endif	
#if defined(CYG_HAL_STARTUP_RAM) && defined(CYG_HAL_USE_ROM_MONITOR)

	# initialize the VSR table
	# We only take control of the interrupt vector,
	# the rest are left to the ROM for now...

	la	a0,__default_interrupt_vsr
	la	a3,hal_vsr_table
	sw	a0,0(a3)
		
#endif
			
#ifdef CYG_HAL_STARTUP_ROM
	# Copy data from ROM to RAM

	.extern	hal_copy_data
	jal	hal_copy_data
	nop
#endif
		
	# Zero BSS

	.extern hal_zero_bss
	jal	hal_zero_bss
	nop

	# Call constructors

	.extern cyg_hal_invoke_constructors
	jal     cyg_hal_invoke_constructors
	nop

	.extern cyg_hal_enable_caches
	jal     cyg_hal_enable_caches
	nop

	.extern cyg_hal_debug_init
	jal     cyg_hal_debug_init
	nop

#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
        .extern initialize_stub
        jal     initialize_stub
        nop
#endif

	# Call cyg_start	
	
	.extern	cyg_start
	jal	cyg_start
	nop

9:	
	j	9b		# Loop if we return
	nop			# (delay slot)
	
	.end	_start	

##-----------------------------------------------------------------------------
## Default exception VSR.
## Saves machine state and calls external handling code.
	
	.globl	__default_exception_vsr
	.ent	__default_exception_vsr
__default_exception_vsr:

	# We enter here with all of the CPU state still
	# in its registers except:
	# K0 = vector index
	# K1 = address of this function

#ifdef CYG_HAL_ROM_MONITOR
	# Switch to interrupt stack to handle exception
	move	k1,sp
	la	sp,__interrupt_stack
#endif
			
	addi	sp,sp,-mips_exception_decrement
				# space for registers + safety margin

	sw	k0,mipsreg_vector(sp)	# store vector

	.set	noat
	# store GPRs
	sw	$0,(mipsreg_regs+0*4)(sp)
	sw	$1,(mipsreg_regs+1*4)(sp)
	sw	$2,(mipsreg_regs+2*4)(sp)
	sw	$3,(mipsreg_regs+3*4)(sp)
	sw	$4,(mipsreg_regs+4*4)(sp)
	sw	$5,(mipsreg_regs+5*4)(sp)
	sw	$6,(mipsreg_regs+6*4)(sp)
	sw	$7,(mipsreg_regs+7*4)(sp)
	sw	$8,(mipsreg_regs+8*4)(sp)
	sw	$9,(mipsreg_regs+9*4)(sp)
	sw	$10,(mipsreg_regs+10*4)(sp)
	sw	$11,(mipsreg_regs+11*4)(sp)
	sw	$12,(mipsreg_regs+12*4)(sp)
	sw	$13,(mipsreg_regs+13*4)(sp)
	sw	$14,(mipsreg_regs+14*4)(sp)
	sw	$15,(mipsreg_regs+15*4)(sp)
	sw	$16,(mipsreg_regs+16*4)(sp)
	sw	$17,(mipsreg_regs+17*4)(sp)
	sw	$18,(mipsreg_regs+18*4)(sp)
	sw	$19,(mipsreg_regs+19*4)(sp)
	sw	$20,(mipsreg_regs+20*4)(sp)
	sw	$21,(mipsreg_regs+21*4)(sp)
	sw	$22,(mipsreg_regs+22*4)(sp)
	sw	$23,(mipsreg_regs+23*4)(sp)
	sw	$24,(mipsreg_regs+24*4)(sp)
	sw	$25,(mipsreg_regs+25*4)(sp)
#	sw	$26,(mipsreg_regs+26*4)(sp)	# == K0
#	sw	$27,(mipsreg_regs+27*4)(sp)	# == K1
	sw	$28,(mipsreg_regs+28*4)(sp)	# == GP
#	sw	$29,(mipsreg_regs+29*4)(sp)	# == SP
	sw	$30,(mipsreg_regs+30*4)(sp)	# == FP
	sw	$31,(mipsreg_regs+31*4)(sp)	# == RA

	mfhi	a0
	mflo	a1
	sw	a0,mipsreg_hi(sp)
	sw	a1,mipsreg_lo(sp)