test1.c

ecos为实时嵌入式操作系统

    CYG_TEST_CHECK( E_OK == ercd, "dly_tsk bad ercd" );
    ercd = dis_dsp();
    CYG_TEST_CHECK( E_OK == ercd, "dis_dsp bad ercd" );
#ifdef CYGSEM_UITRON_BAD_PARAMS_RETURN_ERRORS
    ercd = dly_tsk( 10 );
    CYG_TEST_CHECK( E_CTX == ercd, "dly_tsk bad ercd !E_CTX" );
    ercd = dis_dsp();
    CYG_TEST_CHECK( E_OK == ercd, "dis_dsp bad ercd" );
    ercd = dly_tsk( 10 );
    CYG_TEST_CHECK( E_CTX == ercd, "dly_tsk bad ercd !E_CTX" );
#endif // we can test bad param error returns
    ercd = ena_dsp();
    CYG_TEST_CHECK( E_OK == ercd, "ena_dsp bad ercd" );
    ercd = dly_tsk( 10 );
    CYG_TEST_CHECK( E_OK == ercd, "dly_tsk bad ercd" );
    ercd = ena_dsp();
    CYG_TEST_CHECK( E_OK == ercd, "ena_dsp bad ercd" );
    ercd = dly_tsk( 10 );
    CYG_TEST_CHECK( E_OK == ercd, "dly_tsk bad ercd" );

    CYG_TEST_PASS( "dly_tsk, ena_dsp, dis_dsp" );
    
    CYG_TEST_INFO( "Testing ready queue manipulation" );
    ercd = rot_rdq( 0 );
    CYG_TEST_CHECK( E_OK == ercd, "rot_rdq bad ercd" );
    ercd = rot_rdq( 4 );
    CYG_TEST_CHECK( E_OK == ercd, "rot_rdq bad ercd" );
    ercd = rot_rdq( 5 );
    CYG_TEST_CHECK( E_OK == ercd, "rot_rdq bad ercd" );
#ifdef CYGSEM_UITRON_BAD_PARAMS_RETURN_ERRORS
    ercd = rot_rdq( -6 );
    CYG_TEST_CHECK( E_PAR == ercd, "rot_rdq bad ercd !E_PAR" );
    ercd = rot_rdq( 99 );
    CYG_TEST_CHECK( E_PAR == ercd, "rot_rdq bad ercd !E_PAR" );
#endif // we can test bad param error returns
    
    CYG_TEST_PASS( "rot_rdq" );

    CYG_TEST_INFO( "Testing suspend/resume" );
#ifdef CYGSEM_UITRON_BAD_PARAMS_RETURN_ERRORS
    ercd = sus_tsk( -6 );
    CYG_TEST_CHECK( E_ID == ercd, "sus_tsk bad ercd !E_ID" );
    ercd = sus_tsk( 99 );
    CYG_TEST_CHECK( E_ID == ercd, "sus_tsk bad ercd !E_ID" );
    ercd = rsm_tsk( -6 );
    CYG_TEST_CHECK( E_ID == ercd, "rsm_tsk bad ercd !E_ID" );
    ercd = rsm_tsk( 99 );
    CYG_TEST_CHECK( E_ID == ercd, "rsm_tsk bad ercd !E_ID" );
    ercd = frsm_tsk( -6 );
    CYG_TEST_CHECK( E_ID == ercd, "frsm_tsk bad ercd !E_ID" );
    ercd = frsm_tsk( 99 );
    CYG_TEST_CHECK( E_ID == ercd, "frsm_tsk bad ercd !E_ID" );
#endif // we can test bad param error returns
    // drop task 3 pri to same as us
    CYG_TEST_CHECK( 0 == intercount, "intercount != 0" );

    intercom = 3;                       // tell T3 to loop
    TSRELEASE();
    ercd = dis_dsp();
    CYG_TEST_CHECK( E_OK == ercd, "dis_dsp bad ercd" );
    ercd = sta_tsk( 3, 66 );
    CYG_TEST_CHECK( E_OK == ercd, "sta_tsk bad ercd" );
    ercd = chg_pri( 3, 5 );
    CYG_TEST_CHECK( E_OK == ercd, "chg_pri bad ercd" );
    ercd = ena_dsp();
    CYG_TEST_CHECK( E_OK == ercd, "ena_dsp bad ercd" );

    ercd = rot_rdq( 0 );
    CYG_TEST_CHECK( E_OK == ercd, "rot_rdq bad ercd" );
    ICWAIT( 1 );
    CYG_TEST_CHECK( 1 == intercount, "intercount != 1" );
    ercd = sus_tsk( 3 );
    TSRELEASE();
    CYG_TEST_CHECK( E_OK == ercd, "sus_tsk bad ercd" );
    intercom = 0;                       // bad data to T3
    ercd = rot_rdq( 0 );
    CYG_TEST_CHECK( E_OK == ercd, "rot_rdq bad ercd" );
    CYG_TEST_CHECK( 1 == intercount, "intercount != 1" );
    intercom = 3;                       // tell T3 to loop
    TSRELEASE();
    ercd = rsm_tsk( 3 );
    CYG_TEST_CHECK( E_OK == ercd, "rsm_tsk bad ercd" );
    ercd = rot_rdq( 0 );
    CYG_TEST_CHECK( E_OK == ercd, "rot_rdq bad ercd" );
    ICWAIT( 2 );
    CYG_TEST_CHECK( 2 == intercount, "intercount != 2" );

    CYG_TEST_INFO( "Command task 3 inner loop stop" );
    intercom = 2 + 4;
    TSRELEASE();
    ercd = rot_rdq( 0 );
    CYG_TEST_CHECK( E_OK == ercd, "rot_rdq bad ercd" );
    CYG_TEST_CHECK( 2 == intercount, "intercount != 2" );
    
    ercd = sus_tsk( 3 );
    CYG_TEST_CHECK( E_OK == ercd, "sus_tsk bad ercd" );
    intercom = 0;                       // bad data to T3
    TSRELEASE();
    ercd = rot_rdq( 0 );
    CYG_TEST_CHECK( E_OK == ercd, "rot_rdq bad ercd" );
    ercd = sus_tsk( 3 );                // suspend AGAIN
    CYG_TEST_CHECK( E_OK == ercd, "sus_tsk bad ercd" );
    ercd = sus_tsk( 3 );                //     AND AGAIN
    CYG_TEST_CHECK( E_OK == ercd, "sus_tsk bad ercd" );
    TSRELEASE();
    ercd = rot_rdq( 0 );
    CYG_TEST_CHECK( E_OK == ercd, "rot_rdq bad ercd" );
    CYG_TEST_CHECK( 2 == intercount, "intercount != 2" );
    ercd = rsm_tsk( 3 );
    CYG_TEST_CHECK( E_OK == ercd, "rsm_tsk bad ercd" );
    ercd = rsm_tsk( 3 );
    CYG_TEST_CHECK( E_OK == ercd, "rsm_tsk bad ercd" );
    TSRELEASE();
    ercd = rot_rdq( 0 );
    CYG_TEST_CHECK( E_OK == ercd, "rot_rdq bad ercd" );
    CYG_TEST_CHECK( 2 == intercount, "intercount != 2" );
    intercom = 3;                       // tell T3 to loop
    TSRELEASE();
    ercd = rsm_tsk( 3 );                // expect restart this time
    CYG_TEST_CHECK( E_OK == ercd, "rsm_tsk bad ercd" );
    ercd = rot_rdq( 0 );
    CYG_TEST_CHECK( E_OK == ercd, "rot_rdq bad ercd" );
    ICWAIT( 3 );
    CYG_TEST_CHECK( 3 == intercount, "intercount != 3" );

    CYG_TEST_INFO( "Command task 3 inner loop stop 2" );
    intercom = 2 + 4;
    TSRELEASE();
    ercd = rot_rdq( 0 );
    CYG_TEST_CHECK( E_OK == ercd, "rot_rdq bad ercd" );
    CYG_TEST_CHECK( 3 == intercount, "intercount != 3" );
    
    ercd = sus_tsk( 3 );
    CYG_TEST_CHECK( E_OK == ercd, "sus_tsk bad ercd" );
    intercom = 0;                       // bad data to T3
    TSRELEASE();
    ercd = rot_rdq( 0 );
    CYG_TEST_CHECK( E_OK == ercd, "rot_rdq bad ercd" );
    CYG_TEST_CHECK( 3 == intercount, "intercount != 3" );
    ercd = sus_tsk( 3 );                // suspend AGAIN
    CYG_TEST_CHECK( E_OK == ercd, "sus_tsk bad ercd" );
    ercd = sus_tsk( 3 );                //     AND AGAIN
    CYG_TEST_CHECK( E_OK == ercd, "sus_tsk bad ercd" );
    TSRELEASE();
    ercd = rot_rdq( 0 );
    CYG_TEST_CHECK( E_OK == ercd, "rot_rdq bad ercd" );
    CYG_TEST_CHECK( 3 == intercount, "intercount != 3" );
    intercom = 3;                       // tell T3 to loop
    TSRELEASE();
    ercd = frsm_tsk( 3 );               // expect restart this time
    CYG_TEST_CHECK( E_OK == ercd, "frsm_tsk bad ercd" );
    ercd = rot_rdq( 0 );
    CYG_TEST_CHECK( E_OK == ercd, "rot_rdq bad ercd" );
    ICWAIT( 4 );
    CYG_TEST_CHECK( 4 == intercount, "intercount != 4" );

    TSRELEASE();
    ercd = rsm_tsk( 3 );               // try it again
    CYG_TEST_CHECK( E_OBJ == ercd, "rsm_tsk bad ercd !E_OBJ" );
    ercd = rot_rdq( 0 );
    CYG_TEST_CHECK( E_OK == ercd, "rot_rdq bad ercd" );
    ICWAIT( 5 );
    CYG_TEST_CHECK( 5 == intercount, "intercount != 5" );

    TSRELEASE();
    ercd = frsm_tsk( 3 );               // try it again
    CYG_TEST_CHECK( E_OBJ == ercd, "frsm_tsk bad ercd !E_OBJ" );
    ercd = rot_rdq( 0 );
    CYG_TEST_CHECK( E_OK == ercd, "rot_rdq bad ercd" );
    ICWAIT( 6 );
    CYG_TEST_CHECK( 6 == intercount, "intercount != 6" );

    CYG_TEST_INFO( "Command task 3 all loops stop" );
    intercom = 4 + 8;
    TSRELEASE();
    ercd = rot_rdq( 0 );
    CYG_TEST_CHECK( E_OK == ercd, "rot_rdq bad ercd" );
    TSRELEASE();
    ercd = rot_rdq( 0 );
    CYG_TEST_CHECK( E_OK == ercd, "rot_rdq bad ercd" );
    CYG_TEST_CHECK( 6 == intercount, "intercount != 6" );
    
    intercom = intercount = 0;

    CYG_TEST_PASS( "sus_tsk, rsm_tsk, frsm_tsk" );

    CYG_TEST_INFO( "Testing sleep/wakeup stuff" );
#ifdef CYGSEM_UITRON_BAD_PARAMS_RETURN_ERRORS
    ercd = wup_tsk( -6 );
    CYG_TEST_CHECK( E_ID == ercd, "wup_tsk bad ercd !E_ID" );
    ercd = wup_tsk( 99 );
    CYG_TEST_CHECK( E_ID == ercd, "wup_tsk bad ercd !E_ID" );
    ercd = can_wup( &scratch, -6 );
    CYG_TEST_CHECK( E_ID == ercd, "can_wup bad ercd !E_ID" );
    ercd = can_wup( &scratch, 99 );
    CYG_TEST_CHECK( E_ID == ercd, "can_wup bad ercd !E_ID" );
#ifndef CYGSEM_UITRON_PARAMS_NULL_IS_GOOD_PTR
    ercd = can_wup( NULL, 2 );
    CYG_TEST_CHECK( E_PAR == ercd, "can_wup bad ercd !E_PAR" );
#endif
    ercd = can_wup( NADR, 2 );
    CYG_TEST_CHECK( E_PAR == ercd, "can_wup bad ercd !E_PAR" );
    
    ercd = wup_tsk( 0 );                // not ourself
    CYG_TEST_CHECK( E_ID == ercd, "wup_tsk bad ercd !E_ID" );
    ercd = wup_tsk( 1 );                // ourself
    CYG_TEST_CHECK( E_OBJ == ercd, "wup_tsk bad ercd !E_OBJ" );
#endif // we can test bad param error returns

#ifdef CYGSEM_UITRON_BAD_PARAMS_RETURN_ERRORS
    ercd = tslp_tsk( -6 );
    CYG_TEST_CHECK( E_PAR == ercd, "tslp_tsk bad ercd !E_PAR" );
#endif // we can test bad param error returns
    ercd = tslp_tsk( TMO_POL );
    CYG_TEST_CHECK( E_TMOUT == ercd, "tslp_tsk bad ercd !E_TMOUT" );
    ercd = tslp_tsk( 5 );
    CYG_TEST_CHECK( E_TMOUT == ercd, "tslp_tsk bad ercd !E_TMOUT" );
#ifdef CYGSEM_UITRON_BAD_PARAMS_RETURN_ERRORS
    ercd = dis_dsp();
    CYG_TEST_CHECK( E_OK == ercd, "dis_dsp bad ercd" );
    ercd = tslp_tsk( TMO_FEVR );
    CYG_TEST_CHECK( E_CTX == ercd, "tslp_tsk bad ercd !E_CTX" );
     ercd = tslp_tsk( TMO_POL );
    CYG_TEST_CHECK( E_CTX == ercd, "tslp_tsk bad ercd !E_CTX" );
    ercd = tslp_tsk( 5 );
    CYG_TEST_CHECK( E_CTX == ercd, "tslp_tsk bad ercd !E_CTX" );
    ercd = ena_dsp();
    CYG_TEST_CHECK( E_OK == ercd, "ena_dsp bad ercd" );
    ercd = tslp_tsk( -6 );
    CYG_TEST_CHECK( E_PAR == ercd, "tslp_tsk bad ercd !E_PAR" );
#endif // we can test bad param error returns
    ercd = tslp_tsk( TMO_POL );
    CYG_TEST_CHECK( E_TMOUT == ercd, "tslp_tsk bad ercd !E_TMOUT" );
    ercd = tslp_tsk( 5 );
    CYG_TEST_CHECK( E_TMOUT == ercd, "tslp_tsk bad ercd !E_TMOUT" );

    // drop task 4 pri to same as us
    intercount = 0;
    intercom = 1;                       // test plain slp_tsk
    TSRELEASE();
    ercd = chg_pri( 4, 5 );
    CYG_TEST_CHECK( E_OBJ == ercd, "chg_pri bad ercd" );

    ercd = dis_dsp();
    CYG_TEST_CHECK( E_OK == ercd, "dis_dsp bad ercd" );
    ercd = sta_tsk( 4, 77 );
    CYG_TEST_CHECK( E_OK == ercd, "sta_tsk bad ercd" );
    ercd = chg_pri( 4, 5 );
    CYG_TEST_CHECK( E_OK == ercd, "chg_pri bad ercd" );
    ercd = ena_dsp();
    CYG_TEST_CHECK( E_OK == ercd, "ena_dsp bad ercd" );

    ercd = wup_tsk( 4 );
    CYG_TEST_CHECK( E_OK == ercd, "wup_tsk bad ercd" );
    ercd = rot_rdq( 0 );
    CYG_TEST_CHECK( E_OK == ercd, "rot_rdq bad ercd" );
    ICWAIT( 1 );
    CYG_TEST_CHECK( 1 == intercount, "intercount != 1" );
    intercom = 2;                       // test tslp_tsk
    TSRELEASE();
    ercd = wup_tsk( 4 );
    CYG_TEST_CHECK( E_OK == ercd, "wup_tsk bad ercd" );
    ercd = rot_rdq( 0 );
    CYG_TEST_CHECK( E_OK == ercd, "rot_rdq bad ercd" );
    ICWAIT( 2 );
    CYG_TEST_CHECK( 2 == intercount, "intercount != 2" );
    intercom = 3;                       // test tslp_tsk
    TSRELEASE();
    ercd = rot_rdq( 0 );