📄 address.h
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/* address.h */
/* This head file include all address definition of DSP reading or writing perpheral*/
/*********************************************************************************/
/* EMIF_CE1 address range is between 9000 0000 and 9FFF FFFF */
/* In the CPLD among CE1 address space the address[21:19]=000b is assigned to */
/* ADV601_CS. */
#define ADV601_CS_ADDR 0xa0000000
#define ADV601_DIR_REG0_ADDR 0xa0000000
#define ADV601_DIR_REG1_ADDR 0xa0000004
#define ADV601_DIR_REG2_ADDR 0xa0000008
#define ADV601_DIR_REG3_ADDR 0xa000000c
#define ADV601_INDIR_REG0_ADDR 0x0 /*model control register*/
#define ADV601_INDIR_REG1_ADDR 0x1 /*FIFO control register*/
#define ADV601_INDIR_REG2_ADDR 0x2 /*HSTART register*/
#define ADV601_INDIR_REG3_ADDR 0x3 /*HEND register*/
#define ADV601_INDIR_REG4_ADDR 0x4 /*VSTART register*/
#define ADV601_INDIR_REG5_ADDR 0x5 /*VEND register*/
#define ADV601_INDIR_REG6_ADDR 0x80 /*the start address of sum of squares*/
#define ADV601_INDIR_REG7_ADDR 0xa9 /*the end address of sum of squares*/
#define ADV601_INDIR_REG8_ADDR 0xaa /*sum of luma register*/
#define ADV601_INDIR_REG9_ADDR 0xab /*sum of Cb register*/
#define ADV601_INDIR_REG10_ADDR 0xac /*sum of Cr register*/
#define ADV601_INDIR_REG11_ADDR 0xad /*min luma register*/
#define ADV601_INDIR_REG12_ADDR 0xae /*max luma register*/
#define ADV601_INDIR_REG13_ADDR 0xaf /*min Cb register*/
#define ADV601_INDIR_REG14_ADDR 0xb0 /*max Cb register*/
#define ADV601_INDIR_REG15_ADDR 0xb1 /*min Cr register*/
#define ADV601_INDIR_REG16_ADDR 0xb2 /*max Cr register*/
#define ADV601_INDIR_REG17_ADDR 0x100 /*the start address of RBW0*/
#define ADV601_INDIR_REG18_ADDR 0x101 /*the start address of BW0*/
#define ADV601_INDIR_REG19_ADDR 0x152 /*the end address of RBW41*/
#define ADV601_INDIR_REG20_ADDR 0x153 /*the end address of BW41*/
/*********************************************************************************/
/* when CPLD_INT1 interrupt TMS320C6211 ,TMS320C6211 should read the state of */
/* ADV601_LCODE and ADV601_STATES_R and ADV601_FIFO_SRQ. In CE1 address space */
/* address[21:19]=001b is assigned for it. when these address are valid, ADV601_CS)*/
/* is invalid, so ADV601 databus show "z" state. CPLD drive data bus. */
#define ADV601_STATE_ADDR 0xa0080000
/*********************************************************************************/
/*when power on , TMS320C6211 should read RATIO_CTR_ADDR for ratio control word */
/*in the CE1 space ,address[21:19]=010 is assigned for reading control word */
#define RATIO_CTR_ADDR 0xa0100000
/*********************************************************************************/
/* In CE1 space the address[21:19]=011 is assigned for UART_CS. */
#define UART_CS_ADDR 0xa0018000
/*********************************************************************************/
/* The CE3 address space is assigned for FLASH_CS */
/*#define FLASH_CS_ADDR */
/*********************************************************************************/
/*In CE1 address space , address[21:19]=100b is assigned for USB_CS */
#define USB_CS_ADDR 0xa0200000
/*********************************************************************************/
/******define EMIF register address***********************************************/
#define EMIF_GBLCTL_ADDR 0x01800000 /*EMIF global control register */
#define EMIF_CECTL1_ADDR 0x01800004 /*EMIF CE1 space control register*/
#define EMIF_CECTL0_ADDR 0x01800008 /*EMIF CE0 space control register*/
#define EMIF_CECTL2_ADDR 0x01800010 /*EMIF CE2 space control register*/
#define EMIF_CECTL3_ADDR 0x01800014 /*EMIF CE3 space control register*/
#define EMIF_SDCTL_ADDR 0x01800018 /*EMIF SDRAM control register */
#define EMIF_SDTIM_ADDR 0x0180001c /*EMIF SDRAM refresh control */
#define EMIF_SDEXT_ADDR 0x01800020 /*EMIF SDRAM extend register */
/**********************************************************************************/
/******cache register address****************************************************/
#define Cache_CCFG_ADDR 0x01840000 /*Cache configuration register */
#define Cache_L2FBAR_ADDR 0x01844000 /*L2 flush base address register*/
#define Cache_L2FWC_ADDR 0x01844004 /*L2 flush word cont register */
#define Cache_L2CBAR_ADDR 0x01844010 /*L2 cache base address register*/
#define Cache_L2CWC_ADDR 0x01844014 /*L2 clean word count register */
#define Cache_L1PFBAR_ADDR 0x01844020 /*L1P flush base address register*/
#define Cache_L1PFWC_ADDR 0x01844024 /*L1P flush word count register */
#define Cache_L1DFBAR_ADDR 0x01844030 /*L1D flush base address register*/
#define Cache_L1DFWC_ADDR 0x01844034 /*L1D flush word count register*/
#define Cache_L2FLUSH_ADDR 0x01845000 /*L2 flush register */
#define Cache_L2CLEAN_ADDR 0x01845004 /*L2 clean register */
#define MAR0_ADDR 0x01848200 /*control CE0 range 80000000-80ffffff*/
#define MAR1_ADDR 0x01848204 /*control CE0 range 81000000-81ffffff*/
#define MAR2_ADDR 0x01848208 /*control CE0 range 82000000-82ffffff*/
#define MAR3_ADDR 0x0184820c /*control CE0 range 83000000-83ffffff*/
#define MAR4_ADDR 0x01848240 /*control CE1 range 90000000-90ffffff*/
#define MAR5_ADDR 0x01848244 /*control CE1 range 91000000-91ffffff*/
#define MAR6_ADDR 0x01848248 /*control CE1 range 92000000-92ffffff*/
#define MAR7_ADDR 0x0184824c /*control CE1 range 93000000-93ffffff*/
#define MAR8_ADDR 0x01848280 /*control CE2 range a0000000-a0ffffff*/
#define MAR9_ADDR 0x01848284 /*control CE2 range a1000000-a1ffffff*/
#define MAR10_ADDR 0x01848288 /*control CE2 range a2000000-a2ffffff*/
#define MAR11_ADDR 0x0184828c /*control CE2 range a3000000-a3ffffff*/
#define MAR12_ADDR 0x018482c0 /*control CE3 range b0000000-b0ffffff*/
#define MAR13_ADDR 0x018482c4 /*control CE3 range b1000000-b1ffffff*/
#define MAR14_ADDR 0x018482c8 /*control CE3 range b2000000-b2ffffff*/
#define MAR15_ADDR 0x018482cc /*control CE3 range b3000000-b3ffffff*/
/*************************************************************************************/
/****EDMA register*******************************************************************/
#define EDMA_PQSR_ADDR 0x01a0ffe0 /*EDMA priority queue status register*/
#define EDMA_CIPR_ADDR 0x01a0ffe4 /*EDMA channel interrupt pending register*/
#define EDMA_CIER_ADDR 0x01a0ffe8 /*EDMA channel interrupt enable register*/
#define EDMA_CCER_ADDR 0x01a0ffec /*EDMA channel chain enable register*/
#define EDMA_ER_ADDR 0x01a0fff0 /*EDMA event register*/
#define EDMA_EER_ADDR 0x01a0fff4 /*EDMA event enable register*/
#define EDMA_ECR_ADDR 0x01a0fff8 /*EDMA event clear register*/
#define EDMA_ESR_ADDR 0x01a0fffc /*EDMA event set register*/
/************************************************************************************/
/****EDMA parameter RAM start address***********************************************/
#define ParaForEvent0_start 0x01a00000 /*the start address of event 0 parameter*/
#define ParaForEvent1_start 0x01a00018 /*the start address of event 1 parameter*/
#define ParaForEvent2_start 0x01a00030 /*the start address of event 2 parameter*/
#define ParaForEvent3_start 0x01a00048 /*the start address of event 3 parameter*/
#define ParaForEvent4_start 0x01a00060 /*the start address of event 4 parameter*/
#define ParaForEvent5_start 0x01a00078 /*the start address of event 5 parameter*/
#define ParaForEvent6_start 0x01a00090 /*the start address of event 6 parameter*/
#define ParaForEvent7_start 0x01a000a8 /*the start address of event 7 parameter*/
#define ParaForEvent8_start 0x01a000c0 /*the start address of event 8 parameter*/
#define ParaForEvent9_start 0x01a000d8 /*the start address of event 9 parameter*/
#define ParaForEvent10_start 0x01a000f0 /*the start address of event 10 parameter*/
#define ParaForEvent11_start 0x01a00108 /*the start address of event 11 parameter*/
#define ParaForEvent12_start 0x01a00120 /*the start address of event 12 parameter*/
#define ParaForEvent13_start 0x01a00138 /*the start address of event 13 parameter*/
#define ParaForEvent14_start 0x01a00150 /*the start address of event 14 parameter*/
#define ParaForEvent15_start 0x01a00168 /*the start address of event 15 parameter*/
#define ReloadForEventM_start 0x01a00180 /*reload/link parameter for event M*/
#define ReloadForEventN_start 0x01a00198 /*relaod/link parameter for event N*/
/***************************************************************************************/
/*****QDMA and Pseudo Register********************************************************/
#define QDMA_QOPT_ADDR 0x02000000 /*QDMA option parameter register*/
#define QDMA_QSRC_ADDR 0x02000004 /*QDMA source address register*/
#define QDMA_QCNT_ADDR 0x02000008 /*QDMA frame count register*/
#define QDMA_QDST_ADDR 0x0200000c /*QDMA destination address register*/
#define QDMA_QIDX_ADDR 0x02000010 /*QDMA index register*/
#define QDMA_QSOPT_ADDR 0x02000020 /*QDMA pseudo option register*/
#define QDMA_QSSRC_ADDR 0x02000024 /*QDMA pseudo source address register*/
#define QDMA_QSCNT_ADDR 0x02000028 /*QDMA pseudo frame count register*/
#define QDMA_QSDST_ADDR 0x0200002c /*QDMA pseudo destination address register*/
#define QDMA_QSIDX_ADDR 0x02000030 /*QDMA pseudo index register*/
/*********************************************************************************/
/***Interrupt selector register****************************************************/
//#define MUXH_ADDR 0x019c0000 /*interrupt multiplexer high*/
//#define MUXL_ADDR 0x019c0004 /*interrupt multiplexer low*/
//#define EXTPOL_ADDR 0x019c0008 /*external interrupt polarity*/
/*********************************************************************************/
/*****McBsp0 register************************************************************/
#define McBSP_DRR0_ADDR 0x018c0000 /*McBSP0 data receive register via peripheral bus*/
#define McBSP_DRR0_EDMA_ADDR 0x30000000 /*McBSP0 data receive register via EDMA bus**/
#define McBSP_DXR0_ADDR 0x018c0004 /*McBSP0 data transmit register via peripheral bus*/
#define McBSP_DXR0_EDMA_ADDR 0x30000000 /*McBSP0 data transmit register via EDMA bus*/
#define McBSP_SPCR0_ADDR 0x018c0008 /*McBSP0 serial port control register*/
#define McBSP_RCR0_ADDR 0x018c000c /*McBSP0 receive control register*/
#define McBSP_XCR0_ADDR 0x018c0010 /*McBSP0 transmit control register*/
#define McBSP_SRGR0_ADDR 0x018c0014 /*McBSP0 sample rate generator register*/
#define McBSP_MCR0_ADDR 0x018c0018 /*McBSP0 mutichannel control register*/
#define McBSP_RCER0_ADDR 0x018c001c /*McBSP0 receive channel enabel register*/
#define McBSP_XCER0_ADDR 0x018c0020 /*McBSP0 transmit channel enable register*/
#define McBSP_PCR0_ADDR 0x018c0024 /*McBSP0 pin control register*/
/********************************************************************************/
/****McBSP1 register************************************************************/
#define McBSP_DRR1_ADDR 0x01900000 /*McBSP1 data receive register via peripheral bus*/
#define McBSP_DRR1_EDMA_ADDR 0x34000000 /*McBSP1 data receive register via EDMA bus*/
#define McBSP_DXR1_ADDR 0x01900004 /*McBSP1 data transmit register via peripheral bus*/
#define McBSP_DXR1_EDMA_ADDR 0x34000000 /*McBSP1 data transmit register via EDMA bus*/
#define McBSP_SPCR1_ADDR 0x01900008 /*McBSP1 serial port control register*/
#define McBSP_RCR1_ADDR 0x0190000c /*McBSP1 receive control register*/
#define McBSP_XCR1_ADDR 0x01900010 /*McBSP1 transmit control register*/
#define McBSP_SRGR1_ADDR 0x01900014 /*McBSP1 sample rate generator register*/
#define McBSP_MCR1_ADDR 0x01900018 /*McBSP1 multichannel control register*/
#define McBSP_RCER1_ADDR 0x0190001c /*McBSP1 receive channel enable register*/
#define McBSP_XCER1_ADDR 0x01900020 /*McBSP1 transmit channel enable register*/
#define McBSP_PCR1_ADDR 0x01900024 /*McBSP1 pin control register*/
/************************************************************************************/
/****Timer 0 register**********************************************************/
#define Timer0_CTL0_ADDR 0x01940000 /*Timer 0 control register*/
#define Timer0_PRD0_ADDR 0x01940004 /*Timer 0 period register*/
#define Timer0_CNT0_ADDR 0x01940008 /*Timer 0 counter register*/
/*******************************************************************************/
/****Timer 1 register **********************************************************/
#define Timer1_CTL1_ADDR 0x01980000 /*Timer 1 control register*/
#define Timer1_PRD1_ADDR 0x01980004 /*Timer 1 period register*/
#define Timer1_CNT1_ADDR 0x01980008 /*Timer 1 counter register*/
/*******************************************************************************/
/****Interrupt Register*********************************************************/
//#define ExterInterPolar_ADDR 0x019C0008 /*external interrupt polarity */
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