📄 dma.h
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#define FRAME_INDEX 16
#define FRAME_INDEX_SZ 16
/* DMA Global Address Register Bits */
#define SPLIT_ADDRESS 3
#define SPLIT_ADDRESS_SZ 29
/* DMA Auxiliary Control Register Bits */
#define CH_PRI 0
#define CH_PRI_SZ 4
#define AUXPRI 4
/*----------------------------------------------------------------------------*/
/* DEFINES */
/*----------------------------------------------------------------------------*/
#define DMA_CH0 0x00
#define DMA_CH1 0x01
#define DMA_CH2 0x02
#define DMA_CH3 0x03
/** BITFIELD VALUES **/
/* DMA Channel Primary Control Register bitfield values */
/* START */
#define DMA_STOP_VAL 0x00
#define DMA_START_VAL 0x01
#define DMA_PAUSE_VAL 0x02
#define DMA_AUTO_START_VAL 0x03
/* SRC DIR, DST DIR */
#define DMA_ADDR_NO_MOD 0x00
#define DMA_ADDR_INC 0x01
#define DMA_ADDR_DEC 0x02
#define DMA_ADDR_INDX 0x03
/* Synchronization Event Numbers */
#define SEN_NONE 0x00
#define SEN_TINT0 0x01
#define SEN_TINT1 0x02
#define SEN_SD_INT 0x03
#define SEN_EXT_INT4 0x04
#define SEN_EXT_INT5 0x05
#define SEN_EXT_INT6 0x06
#define SEN_EXT_INT7 0x07
#define SEN_DMA_INT0 0x08
#define SEN_DMA_INT1 0x09
#define SEN_DMA_INT2 0x0A
#define SEN_DMA_INT3 0x0B
#define SEN_XEVT0 0x0C
#define SEN_REVT0 0x0D
#define SEN_XEVT1 0x0E
#define SEN_REVT1 0x0F
#define SEN_DSPINT 0x10
/* ESIZE defines */
#define DMA_ESIZE32 0x00
#define DMA_ESIZE16 0x01
#define DMA_ESIZE8 0x02
/* PRI defines */
#define DMA_CPU_PRI 0x00
#define DMA_DMA_PRI 0x01
/* SPLIT mode operation defines */
#define DMA_SPLIT_DIS 0x00
#define DMA_SPLIT_GARA 0x01
#define DMA_SPLIT_GARB 0x02
#define DMA_SPLIT_GARC 0x03
/* CNT RELOAD defines */
#define DMA_CNT_RELOADA 0x00
#define DMA_CNT_RELOADB 0x01
/* INDEX defines */
#define DMA_INDXA 0x00
#define DMA_INDXB 0x01
/* EMULATION MODE response defines */
#define DMA_NO_EM_HALT 0x00
#define DMA_EM_HALT 0x01
/* SRC/DST RELOAD defines */
#define DMA_RELOAD_NONE 0x00
#define DMA_RELOAD_GARB 0x01
#define DMA_RELOAD_GARC 0x02
#define DMA_RELOAD_GARD 0x03
/* DMA Channel Primary Control Register bitfield values */
/* DMAC EN Control */
#define DMAC_LO 0x00
#define DMAC_HI 0x01
#define DMAC_RSYNC_STAT 0x02
#define DMAC_WSYNC_STAT 0x03
#define DMAC_FRAME_COND 0x04
#define DMAC_BLOCK_COND 0x05
/*----------------------------------------------------------------------------*/
/* MACRO DEFINITIONS */
/*----------------------------------------------------------------------------*/
#define DMA_START(chan) \
LOAD_FIELD(DMA_PRIMARY_CTRL_ADDR(chan),DMA_START_VAL,START,START_SZ)
#define DMA_AUTO_START(chan) \
LOAD_FIELD(DMA_PRIMARY_CTRL_ADDR(chan),DMA_AUTO_START_VAL,START,START_SZ)
#define DMA_STOP(chan) \
LOAD_FIELD(DMA_PRIMARY_CTRL_ADDR(chan),DMA_STOP_VAL,START,START_SZ)
#define DMA_PAUSE(chan) \
LOAD_FIELD(DMA_PRIMARY_CTRL_ADDR(chan),DMA_PAUSE_VAL,START,START_SZ)
#define DMA_RSYNC_CLR(chan) \
LOAD_FIELD(DMA_SECONDARY_CTRL_ADDR(chan),2,RSYNC_STAT,2)
#define DMA_WSYNC_CLR(chan) \
LOAD_FIELD(DMA_SECONDARY_CTRL_ADDR(chan),2,WSYNC_STAT,2)
#define DMA_RSYNC_SET(chan) \
LOAD_FIELD(DMA_SECONDARY_CTRL_ADDR(chan),1,RSYNC_STAT,2)
#define DMA_WSYNC_SET(chan) \
LOAD_FIELD(DMA_SECONDARY_CTRL_ADDR(chan),1,WSYNC_STAT,2)
/*-----------------------------------------------------------------------------*/
/* FUNCTION DEFINITIONS */
/*-----------------------------------------------------------------------------*/
/******************************************************************************/
/* DMA_INIT - Initialize channel specific control registers. */
/* */
/* This function is responsible for setting the primary control register, */
/* secondary control register, source address, destination address and */
/* transfer count for the specified DMA channel. */
/* */
/******************************************************************************/
__INLINE void dma_init( /*RET: OK or ERROR (invalid channel) */
unsigned short chan, /*IN: DMA channel number */
unsigned int pri_ctrl, /*IN: Value to set primary cntl reg */
unsigned int sec_ctrl, /*IN: Value to set sec cntl reg */
unsigned int src_addr, /*IN: Value to set source addr reg */
unsigned int dst_addr, /*IN: Value to set dest addr reg */
unsigned int trans_ctr /*IN: Value to set transfer counter */
);
/******************************************************************************/
/* DMA_GLOBAL_INIT - Initialize global control registers. */
/* */
/* This function is responsible for setting the DMA auxiliary control */
/* register, global count reload registers A & B, global index registers */
/* A & B, and global address registers A-D. */
/* */
/******************************************************************************/
__INLINE void dma_global_init( /*RET: VOID function */
unsigned int auxcr, /*IN:Value for Aux Control Register */
unsigned int gcra, /*IN:Value for Global Cnt Reload Reg A*/
unsigned int gcrb, /*IN:Value for Global Cnt Reload Reg B*/
unsigned int gndxa, /*IN:Value for Global Idx Reg A */
unsigned int gndxb, /*IN:Value for Global Idx Reg B */
unsigned int gaddra, /*IN:Value for Global Addr Reg A */
unsigned int gaddrb, /*IN:Value for Global Addr Reg B */
unsigned int gaddrc, /*IN:Value for Global Addr Reg C */
unsigned int gaddrd /*IN:Value for Global Addr Reg D */
);
/******************************************************************************/
/* DMA_RESET - Reset all four DMA channels. */
/* */
/* This function resets the specified DMA channel by initializing */
/* channel control registers to their default values */
/* */
/* */
/******************************************************************************/
__INLINE void dma_reset( void );
#if _INLINE
static inline void dma_init(
unsigned short chan, /*IN: DMA channel number */
unsigned int pri_ctrl, /*IN: Value to set primary cntl reg */
unsigned int sec_ctrl, /*IN: Value to set sec cntl reg */
unsigned int src_addr, /*IN: Value to set source addr reg */
unsigned int dst_addr, /*IN: Value to set dest addr reg */
unsigned int trans_ctr /*IN: Value to set transfer counter */
)
{
*((unsigned int *)(DMA_PRIMARY_CTRL_ADDR(chan))) = pri_ctrl;
*((unsigned int *)(DMA_SECONDARY_CTRL_ADDR(chan))) = sec_ctrl;
*((unsigned int *)(DMA_SRC_ADDR_ADDR(chan))) = src_addr;
*((unsigned int *)(DMA_DEST_ADDR_ADDR(chan))) = dst_addr;
*((unsigned int *)(DMA_XFER_COUNTER_ADDR(chan))) = trans_ctr;
}
static inline void dma_global_init(
unsigned int auxcr, /*IN:Value for Aux Control Register */
unsigned int gcra, /*IN:Value for Global Cnt Reload Reg A*/
unsigned int gcrb, /*IN:Value for Global Cnt Reload Reg B*/
unsigned int gndxa, /*IN:Value for Global Idx Reg A */
unsigned int gndxb, /*IN:Value for Global Idx Reg B */
unsigned int gaddra, /*IN:Value for Global Addr Reg A */
unsigned int gaddrb, /*IN:Value for Global Addr Reg B */
unsigned int gaddrc, /*IN:Value for Global Addr Reg C */
unsigned int gaddrd) /*IN:Value for Global Addr Reg D */
{
DMA_AUXCR = auxcr;
DMA_GCR_A = gcra;
DMA_GCR_B = gcrb;
DMA_GNDX_A = gndxa;
DMA_GNDX_B = gndxb;
DMA_GADDR_A = gaddra;
DMA_GADDR_B = gaddrb;
DMA_GADDR_C = gaddrc;
DMA_GADDR_D = gaddrd;
}
static inline void dma_reset( void )
{
int chan;
for (chan= 0;chan <= DMA_CH3; chan++)
{
*(unsigned int *)(DMA_PRIMARY_CTRL_ADDR(chan)) = 0x00;
*(unsigned int *)(DMA_SECONDARY_CTRL_ADDR(chan)) = 0x80;
*(unsigned int *)(DMA_SRC_ADDR_ADDR(chan)) = 0x00;
*(unsigned int *)(DMA_DEST_ADDR_ADDR(chan)) = 0x00;
*(unsigned int *)(DMA_XFER_COUNTER_ADDR(chan)) = 0x00;
}
DMA_AUXCR = 0x00;
DMA_GCR_A = 0x00;
DMA_GCR_B = 0x00;
DMA_GNDX_A = 0x00;
DMA_GNDX_B = 0x00;
DMA_GADDR_A = 0x00;
DMA_GADDR_B = 0x00;
DMA_GADDR_C = 0x00;
DMA_GADDR_D = 0x00;
}
#endif /* _INLINE */
#ifdef __INLINE
#undef __INLINE
#endif
#endif /* _DMA_H_ */
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