📄 mcbspdrv.h
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/******************************************************************************/
/* DNA PROPRIETARY INFORMATION */
/* (C) Copyright 1997,1998 by DNA Enterprises, Inc. */
/* All rights reserved */
/******************************************************************************/
/* MCBSP_DRV.H - Multichannel Serial Port driver routines header file. */
/* */
/* This module is the device driver for the multichannel buffered serial */
/* ports on the C6x. */
/* */
/* MACRO FUNCTIONS: */
/* */
/* FUNCTIONS: */
/* mcbsp_drv_init() - Init Multi-channel Buffered Serial Port driver */
/* mcbsp_open() - Open indicated McBSP for subsequent calls */
/* mcbsp_close() - Releases port for use by another routine/thread*/
/* mcbsp_config() - Configures MCBSP for operation. */
/* mcbsp_mc_config() - Configures multichannel selection */
/* mcbsp_reset() - Reset MCBSP. */
/* mcbsp_stop() - Stop tx, rx, sample rate and frame sync gens */
/* mcbsp_sync_receive() - Receive a buffer of data,CPU polled & blocking */
/* mcbsp_async_receive() - Receive a buffer of data, DMA and interrupt */
/* mcbsp_sync_send() - Xmit a buffer of data, CPU polled & blocking */
/* mcbsp_async_send() - Xmit a buffer of data, DMA and interrupt driven*/
/* mcbsp_cont_async_send - Continuously Xmit single or ping pong buffer */
/* */
/* REVISION HISTORY: */
/* */
/* DATE DESCRIPTION */
/* ------- ---------------------------------------------------------- */
/* 16JUL98 Added dma_esize to the Mcbsp_dma structure to support */
/* variable DMA element transfer sizes */
/* */
/******************************************************************************/
#ifndef _MCBSPDRV_H_
#define _MCBSPDRV_H_
#include "dma_util.h"
#include "mcbsp.h"
/*----------------------------------------------------------------------------*/
/* DEFINES */
/*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------*/
/* MACRO DEFINITIONS */
/*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------*/
/* TYPEDEFS */
/*----------------------------------------------------------------------------*/
typedef struct Ping_pong_buff_struct
{
unsigned char *p_ping_buff;
unsigned char *p_pong_buff;
unsigned int num_bytes_ping;
unsigned int num_bytes_pong;
unsigned int ping_pong_flag;
}
Ping_pong_buffs;
typedef struct Mcbsp_dma_struct
{
int continuous;
unsigned char dma_esize;
Dma_channel_idx dma_channel_idx;
Dma_gidx_idx dma_gidx_idx;
Dma_gadr_idx dma_gadr_idx;
Dma_gcnt_idx dma_gcnt_idx;
}
Mcbsp_dma;
typedef struct Mcbsp_handle_struct
{
int port; /* port number, 0 or 1,2 */
int state; /* OPEN, BUSY, CLOSED */
Ping_pong_buffs tx; /* transmit ping-pong buffers */
Ping_pong_buffs rx; /* receive ping-pong buffers */
Mcbsp_dma tx_dma; /* dma resources for transmit */
Mcbsp_dma rx_dma; /* dma resources for receive */
}
Mcbsp_handle;
typedef Mcbsp_handle * Mcbsp_dev;
/* function typedefs for read and write callback functions */
typedef void Callback(Mcbsp_dev dev,
int status
);
typedef struct Mcbsp_tx_config_struct
{
unsigned char update; /* Update Tx Parameters? T/F */
unsigned char interrupt_mode; /* SPCR(2):XRDY,Blk,Frame,SyncErr */
unsigned char clock_polarity; /* PCR(1): Rise or Fall of CLKX */
unsigned char frame_sync_polarity; /* PCR(1): Active High or Low */
unsigned char clock_mode; /* PCR(1): External or Internal */
unsigned char frame_sync_mode; /* PCR(1): External or Internal */
unsigned char phase_mode; /* XCR(1): Single or Dual */
unsigned char frame_length1; /* XCR(7): 1 to 128 wpf for phase 1*/
unsigned char frame_length2; /* XCR(7): " " phase 2*/
unsigned char word_length1; /* XCR(3): bits per phase 1 word */
unsigned char word_length2; /* XCR(3): bits per phase 2 word */
unsigned char companding; /* XCR(2): ALAW ULAW or MSB or LSB */
unsigned char frame_ignore; /* XCR(1): T/F */
unsigned char data_delay; /* XCR(3): 0-2 Tx data delay */
unsigned char dummy[2]; /* pad bytes to 32 bit align */
}
Mcbsp_tx_config;
typedef struct Mcbsp_rx_config_struct
{
unsigned char update; /* Update Rx Parameters? T/F */
unsigned char interrupt_mode; /* SPCR(2): RRDY,Blk,Frame,Syncerr */
unsigned char justification; /* SPCR(2): RJZF, RJSE or LJZF */
unsigned char clock_polarity; /* PCR(1): Rise or Fall of CLKX */
unsigned char frame_sync_polarity; /* PCR(1): Active High or Low */
unsigned char clock_mode; /* PCR(1): External or Internal */
unsigned char frame_sync_mode; /* PCR(1): External or Internal */
unsigned char phase_mode; /* XCR(1): Single or Dual */
unsigned char frame_length1; /* XCR(7):1 to 128 wpf for phase 1 */
unsigned char frame_length2; /* XCR(7): " " phase 2*/
unsigned char word_length1; /* XCR(3): bits per phase 1 word */
unsigned char word_length2; /* XCR(3): bits per phase 2 word */
unsigned char companding; /* XCR(2): ALAW ULAW or MSB or LSB */
unsigned char frame_ignore; /* XCR(1): T/F */
unsigned char data_delay; /* XCR(3): 0-2 Rx data delay */
unsigned char dummy; /* pad bytes */
}
Mcbsp_rx_config;
typedef struct Mcbsp_srg_config_struct
{
unsigned char update; /* Update SRGR Parameters? T/F */
unsigned char clock_sync; /* SRGR(1):GSYNC_OFF or GSYNC_ON */
unsigned char clks_polarity; /* SRGR(1):rising or falling edge */
unsigned char clks_mode; /* SRGR(1):external or internal */
unsigned char frame_sync_mode; /* SRGR(1):FSX due to DXR-XSR, FSG */
unsigned short frame_period; /* SRGR(12): Frame period 1-4096 */
unsigned char frame_width; /* SRGR(8): 1 to 256 CLKG periods */
unsigned char clock_divider; /* SRGR(8): SRGR clock dvdr: 1-256 */
}
Mcbsp_srg_config;
typedef struct Mcbsp_config_struct
{
unsigned int loopback; /* SPCR(1): TRUE or FALSE */
Mcbsp_tx_config tx;
Mcbsp_rx_config rx;
Mcbsp_srg_config srg;
}
Mcbsp_config;
typedef struct Mcbsp_mc_config_struct
{
unsigned char rx_mc_sel_en; /* MCCR(1): TRUE or FALSE */
unsigned char rx_blockA; /* MCCR(2): rx block 1,3,5 or 7 sel */
unsigned char rx_blockB; /* MCCR(2): rx block 0,2,4 or 6 sel */
unsigned char dummy1; /* pad bytes to 32 bit align */
unsigned short rx_blockA_ch_en; /* RCER(16): 16 chan enable bitmask */
unsigned short rx_blockB_ch_en; /* RCER(16): 16 chan enable bitmask */
unsigned char tx_mc_sel_en; /* MCCR(2): enable, masking modes */
unsigned char tx_blockA; /* MCCR(2): tx block 1,3,5 or 7 sel */
unsigned char tx_blockB; /* MCCR(2): tx block 0,2,4 or 6 sel */
unsigned char dummy2; /* pad bytes to 32 bit align */
unsigned short tx_blockA_ch_en; /* XCER(16): 16 chan enable bitmask */
unsigned short tx_blockB_ch_en; /* XCER(16): 16 chan enable bitmask */
}
Mcbsp_mc_config;
/*-----------------------------------------------------------------------------*/
/* FUNCTION DECLARATIONS */
/*-----------------------------------------------------------------------------*/
/******************************************************************************/
/* MCBSP_DRV_INIT - Initialize MCBSP driver for use. */
/* */
/* This function is responsible for initializing the MCBSP driver. Memory */
/* is allocated for the MCBSP handle structures This */
/* function must be called once before any other MCBSP calls. */
/* */
/******************************************************************************/
int mcbsp_drv_init(void); /* RET: OK or ERROR if mallocs fail */
/******************************************************************************/
/* MCBSP_OPEN - Open a MCBSP port for use. */
/* */
/* This function opens the indicated port by returning a pointer to the */
/* MCBSP_HANDLE used for subsequent McBSP operations. */
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