📄 gpif.c
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// TRIG_WR 1 1 1 1 1 1 1 0
// UNUSED2 1 1 1 1 1 1 1 0
// UNUSED3 1 1 1 1 1 1 1 0
// UNUSED4 1 1 1 1 1 1 1 0
// UNUSED5 1 1 1 1 1 1 1 0
//
// END DO NOT EDIT
// GPIF Program Code
// DO NOT EDIT ...
#include "fx2.h"
#include "fx2regs.h"
// END DO NOT EDIT
// DO NOT EDIT ...
const char xdata WaveData[128] =
{
// Wave 0
/* LenBr */ 0x01, 0x02, 0x03, 0x3F, 0x04, 0x04, 0x04, 0x07,
/* Opcode*/ 0x00, 0x02, 0x02, 0x0B, 0x00, 0x00, 0x10, 0x00,
/* Output*/ 0xFF, 0xFD, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0,
/* LFun */ 0x00, 0x09, 0x12, 0x1B, 0x1B, 0x2D, 0x3F, 0x3F,
// Wave 1
/* LenBr */ 0x01, 0x02, 0x03, 0x3F, 0x04, 0x04, 0x04, 0x07,
/* Opcode*/ 0x08, 0x02, 0x00, 0x01, 0x00, 0x00, 0x10, 0x00,
/* Output*/ 0xFF, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0,
/* LFun */ 0x00, 0x12, 0x1B, 0x1B, 0x1B, 0x2D, 0x3F, 0x3F,
// Wave 2
/* LenBr */ 0x04, 0x03, 0x01, 0x3F, 0x20, 0x20, 0x20, 0x07,
/* Opcode*/ 0x02, 0x02, 0x02, 0x0D, 0x00, 0x00, 0x00, 0x00,
/* Output*/ 0xFF, 0xFD, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0,
/* LFun */ 0x09, 0x09, 0x1B, 0x1B, 0x00, 0x2D, 0x36, 0x3F,
// Wave 3
/* LenBr */ 0x04, 0x03, 0x02, 0x3F, 0x20, 0x20, 0x20, 0x07,
/* Opcode*/ 0x00, 0x02, 0x04, 0x09, 0x00, 0x00, 0x00, 0x00,
/* Output*/ 0xFF, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0,
/* LFun */ 0x12, 0x09, 0x1B, 0x1B, 0x00, 0x2D, 0x36, 0x3F
};
// END DO NOT EDIT
// DO NOT EDIT ...
const char xdata InitData[7] =
{
/* Regs */ 0x00,0x00,0x00,0xC0,0x06,0x1B,0x11
};
// END DO NOT EDIT
// TO DO: You may add additional code below.
void GpifInit( void )
{
BYTE i;
// 8051 doesn't have access to waveform memories 'til
// the part is in GPIF mode.
IFCONFIG = 0xCE; // IFCLKSRC=1 , GPIF executes on internal clk source
// xMHz=1 , 48MHz internal clk rate
// IFCLKOE=0 , Don't drive IFCLK pin signal at 48MHz
// IFCLKPOL=0 , Don't invert IFCLK pin signal from internal clk
// ASYNC=1 , GPIF samples asynchronous to IFCLK
// GSTATE=1 , Drive GPIF states out on PORTE[2:0], debug WF
// IFCFG[1:0]=10, FX2 in GPIF mode
GPIFABORT = 0xFF; // abort any waveforms pending
// To configure EPx FIFOs, please refer to Slave FIFO TRM Chapter
//FIFORESET = 0xFF; // reset slave FIFOs
// TODO: Configure Slave FIFOs here as per your need.
GPIFREADYCFG = InitData[ 0 ];
GPIFCTLCFG = InitData[ 1 ];
GPIFIDLECS = InitData[ 2 ];
GPIFIDLECTL = InitData[ 3 ];
GPIFWFSELECT = InitData[ 5 ];
GPIFREADYSTAT = InitData[ 6 ];
// TC Expires Not RDY5 Pin feature "bit" polarity swaps from REVB to REVD
// override GPIFTool generated data. (default = enabled)
GPIFREADYCFG |= 0x20; // Don't use TC Expires Not RDY5 Pin feature
// Uncomment the following to use the TC Expires Not RDY5 Pin feature
// GPIFREADYCFG &= ~0x20; // don't use TC Expires Not RDY5 Pin feature
AUTOPTRSETUP = 0x06; // increment both pointers,
// ....on-chip access via SFR versions
// Source
APTR1H = MSB( &WaveData );
APTR1L = LSB( &WaveData );
// Destination
AUTOPTRH2 = 0xE4;
AUTOPTRL2 = 0x00;
// Transfer from source to destination
for ( i = 0x00; i < 128; i++ )
{
XAUTODAT2 = XAUTODAT1;
}
// Now, dual autopointer to scratch ram...
// Source
APTR1H = 0xE4;
APTR1L = 0x00;
// Destination
AUTOPTRH2 = 0xE0;
AUTOPTRL2 = 0x00;
// Transfer from source to Destination
for ( i = 0x00; i < 128; i++ )
{
XAUTODAT2 = XAUTODAT1;
}
// Configure GPIF Address pins, output initial value,
PORTCCFG = 0xFF; // [7:0] as alt. func. GPIFADR[7:0]
OEC = 0x00; // and as outputs
PORTECFG |= 0x80; // [8] as alt. func. GPIFADR[8]
OEC |= 0x80; // and as output
// ...OR... tri-state GPIFADR[8:0] pins
// PORTCCFG = 0x00; // [7:0] as port I/O
// OEC = 0x00; // and as inputs
// PORTECFG &= 0x7F; // [8] as port I/O
// OEC &= 0x7F; // and as input
// GPIF address pins update when GPIFADRH/L written
GPIFADRH = 0x00; // bits[7:1] always 0
GPIFADRL = 0x00; // point to PERIPHERAL address 0x0000
// TODO: change GPIF Address pins to meet your needs
// Initialize UDMA related registers (default values)
FLOWSTATE=0x00; //Defines GPIF flow state
FLOWHOLDOFF=0x00;
FLOWLOGIC=0x00; //Defines flow/hold decision criteria
FLOWEQ0CTL=00; //CTL states during active flow state
FLOWEQ1CTL=0x00; //CTL states during hold flow state
FLOWSTB=0x20; //CTL/RDY Signal to use as master data strobe
FLOWSTBEDGE=0x01; //Defines active master strobe edge
FLOWSTBHPERIOD=0x02; //Half Period of output master strobe
GPIFHOLDAMOUNT=0x00; //Data delay shift
UDMACRCQUAL=0x00; //UDMA In only, host terminated use only
}
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