📄 gpif.lst
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149 // UNUSED4 1 1 1 1 1 1 1 0
150 // UNUSED5 1 1 1 1 1 1 1 0
151 //
152 // END DO NOT EDIT
153
154 // GPIF Program Code
155
156 // DO NOT EDIT ...
157 #include "fx2.h"
158 #include "fx2regs.h"
159 // END DO NOT EDIT
160
161 // DO NOT EDIT ...
162 const char xdata WaveData[128] =
163 {
164 // Wave 0
165 /* LenBr */ 0x01, 0x02, 0x03, 0x3F, 0x04, 0x04, 0x04, 0x07,
166 /* Opcode*/ 0x00, 0x02, 0x02, 0x0B, 0x00, 0x00, 0x10, 0x00,
167 /* Output*/ 0xFF, 0xFD, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0,
168 /* LFun */ 0x00, 0x09, 0x12, 0x1B, 0x1B, 0x2D, 0x3F, 0x3F,
169 // Wave 1
170 /* LenBr */ 0x01, 0x02, 0x03, 0x3F, 0x04, 0x04, 0x04, 0x07,
171 /* Opcode*/ 0x08, 0x02, 0x00, 0x01, 0x00, 0x00, 0x10, 0x00,
172 /* Output*/ 0xFF, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0,
173 /* LFun */ 0x00, 0x12, 0x1B, 0x1B, 0x1B, 0x2D, 0x3F, 0x3F,
174 // Wave 2
175 /* LenBr */ 0x04, 0x03, 0x01, 0x3F, 0x20, 0x20, 0x20, 0x07,
176 /* Opcode*/ 0x02, 0x02, 0x02, 0x0D, 0x00, 0x00, 0x00, 0x00,
177 /* Output*/ 0xFF, 0xFD, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0,
178 /* LFun */ 0x09, 0x09, 0x1B, 0x1B, 0x00, 0x2D, 0x36, 0x3F,
179 // Wave 3
C51 COMPILER V7.00 GPIF 05/20/2003 15:33:06 PAGE 4
180 /* LenBr */ 0x04, 0x03, 0x02, 0x3F, 0x20, 0x20, 0x20, 0x07,
181 /* Opcode*/ 0x00, 0x02, 0x04, 0x09, 0x00, 0x00, 0x00, 0x00,
182 /* Output*/ 0xFF, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0,
183 /* LFun */ 0x12, 0x09, 0x1B, 0x1B, 0x00, 0x2D, 0x36, 0x3F
184 };
185 // END DO NOT EDIT
186
187 // DO NOT EDIT ...
188 const char xdata InitData[7] =
189 {
190 /* Regs */ 0x00,0x00,0x00,0xC0,0x06,0x1B,0x11
191 };
192 // END DO NOT EDIT
193
194 // TO DO: You may add additional code below.
195
196
197 void GpifInit( void )
198 {
199 1 BYTE i;
200 1
201 1 // 8051 doesn't have access to waveform memories 'til
202 1 // the part is in GPIF mode.
203 1 IFCONFIG = 0xCE; // IFCLKSRC=1 , GPIF executes on internal clk source
204 1 // xMHz=1 , 48MHz internal clk rate
205 1 // IFCLKOE=0 , Don't drive IFCLK pin signal at 48MHz
206 1 // IFCLKPOL=0 , Don't invert IFCLK pin signal from internal clk
207 1 // ASYNC=1 , GPIF samples asynchronous to IFCLK
208 1 // GSTATE=1 , Drive GPIF states out on PORTE[2:0], debug WF
209 1 // IFCFG[1:0]=10, FX2 in GPIF mode
210 1
211 1 GPIFABORT = 0xFF; // abort any waveforms pending
212 1
213 1 // To configure EPx FIFOs, please refer to Slave FIFO TRM Chapter
214 1 //FIFORESET = 0xFF; // reset slave FIFOs
215 1
216 1 // TODO: Configure Slave FIFOs here as per your need.
217 1
218 1 GPIFREADYCFG = InitData[ 0 ];
219 1 GPIFCTLCFG = InitData[ 1 ];
220 1 GPIFIDLECS = InitData[ 2 ];
221 1 GPIFIDLECTL = InitData[ 3 ];
222 1 GPIFWFSELECT = InitData[ 5 ];
223 1 GPIFREADYSTAT = InitData[ 6 ];
224 1
225 1
226 1 // TC Expires Not RDY5 Pin feature "bit" polarity swaps from REVB to REVD
227 1 // override GPIFTool generated data. (default = enabled)
228 1 GPIFREADYCFG |= 0x20; // Don't use TC Expires Not RDY5 Pin feature
229 1 // Uncomment the following to use the TC Expires Not RDY5 Pin feature
230 1 // GPIFREADYCFG &= ~0x20; // don't use TC Expires Not RDY5 Pin feature
231 1
232 1 AUTOPTRSETUP = 0x06; // increment both pointers,
233 1 // ....on-chip access via SFR versions
234 1 // Source
235 1 APTR1H = MSB( &WaveData );
236 1 APTR1L = LSB( &WaveData );
237 1 // Destination
238 1 AUTOPTRH2 = 0xE4;
239 1 AUTOPTRL2 = 0x00;
240 1 // Transfer from source to destination
241 1 for ( i = 0x00; i < 128; i++ )
C51 COMPILER V7.00 GPIF 05/20/2003 15:33:06 PAGE 5
242 1 {
243 2 XAUTODAT2 = XAUTODAT1;
244 2 }
245 1
246 1 // Now, dual autopointer to scratch ram...
247 1 // Source
248 1 APTR1H = 0xE4;
249 1 APTR1L = 0x00;
250 1 // Destination
251 1 AUTOPTRH2 = 0xE0;
252 1 AUTOPTRL2 = 0x00;
253 1
254 1 // Transfer from source to Destination
255 1 for ( i = 0x00; i < 128; i++ )
256 1 {
257 2 XAUTODAT2 = XAUTODAT1;
258 2 }
259 1
260 1
261 1
262 1 // Configure GPIF Address pins, output initial value,
263 1 PORTCCFG = 0xFF; // [7:0] as alt. func. GPIFADR[7:0]
264 1 OEC = 0x00; // and as outputs
265 1 PORTECFG |= 0x80; // [8] as alt. func. GPIFADR[8]
266 1 OEC |= 0x80; // and as output
267 1
268 1 // ...OR... tri-state GPIFADR[8:0] pins
269 1 // PORTCCFG = 0x00; // [7:0] as port I/O
270 1 // OEC = 0x00; // and as inputs
271 1 // PORTECFG &= 0x7F; // [8] as port I/O
272 1 // OEC &= 0x7F; // and as input
273 1
274 1 // GPIF address pins update when GPIFADRH/L written
275 1 GPIFADRH = 0x00; // bits[7:1] always 0
276 1 GPIFADRL = 0x00; // point to PERIPHERAL address 0x0000
277 1 // TODO: change GPIF Address pins to meet your needs
278 1
279 1 // Initialize UDMA related registers (default values)
280 1 FLOWSTATE=0x00; //Defines GPIF flow state
281 1 FLOWHOLDOFF=0x00;
282 1 FLOWLOGIC=0x00; //Defines flow/hold decision criteria
283 1 FLOWEQ0CTL=00; //CTL states during active flow state
284 1 FLOWEQ1CTL=0x00; //CTL states during hold flow state
285 1 FLOWSTB=0x20; //CTL/RDY Signal to use as master data strobe
286 1 FLOWSTBEDGE=0x01; //Defines active master strobe edge
287 1 FLOWSTBHPERIOD=0x02; //Half Period of output master strobe
288 1 GPIFHOLDAMOUNT=0x00; //Data delay shift
289 1 UDMACRCQUAL=0x00; //UDMA In only, host terminated use only
290 1 }
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 196 ----
CONSTANT SIZE = ---- ----
XDATA SIZE = 135 ----
PDATA SIZE = ---- ----
DATA SIZE = ---- ----
IDATA SIZE = ---- ----
BIT SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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