📄 gpifburst8a.lst
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474 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
475 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
476 3 break;
477 3 }
478 2 case VX_A9:
479 2 { // Do a FIFO Wr transaction w/TC=BC from EP2
480 3 if( EP24FIFOFLGS & 0x02 )
481 3 { // EP2EF=1 when FIFO is empty, 8051 didn't "pass-on" pkt.
482 4 *EP0BUF = 0x00; // Buffer was empty, not available
483 4 ledX_rdvar = LED3_ON; // Indicate empty buffer while GPIF write transaction
484 4 }
485 3 else
486 3 { // EP2EF=0 when FIFO "not" empty, 8051 committed pkt.
487 4 GPIFTRIG = GPIF_EP2; // R/W=0, EP[1:0]=FIFO_EpNum for EPx write(s)
488 4 *EP0BUF = 0xA9;
489 4 BLINK_LED(); // Succesful transaction
C51 COMPILER V7.00 GPIFBURST8A 05/20/2003 15:33:07 PAGE 9
490 4 }
491 3 EP0BCH = 0;
492 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
493 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
494 3 break;
495 3 }
496 2 case VX_AA:
497 2 { // manually commit IN data to host...
498 3 // GPIF needs to still be pointing to EP8, last FIFO accessed
499 3 if( EP2468STAT & 0x80 )
500 3 { // EP8F=1 when buffer is not available
501 4 *EP0BUF = 0x00; // buffer wasn't available
502 4 ledX_rdvar = LED3_ON; // debug
503 4 }
504 3 else
505 3 { // EP8F=0 when buffer is available
506 4 EP8BCH = EP8FIFOBCH;
507 4 EP8BCL = EP8FIFOBCL; // 8051 commits pkt by writing bc
508 4 ledX_rdvar = LED3_OFF; // debug
509 4 *EP0BUF = 0xAA;
510 4 }
511 3 EP0BCH = 0;
512 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
513 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
514 3 BLINK_LED();
515 3 break;
516 3 }
517 2 case VX_AB:
518 2 { // manually commit OUT data to master...
519 3 // GPIF needs to still be pointing to EP8, last FIFO accessed
520 3 if( EP2468STAT & 0x01 )
521 3 { // EP2EF=1 when FIFO is empty, host didn't sent pkt.
522 4 *EP0BUF = 0x00; // buffer was empty, not available
523 4 ledX_rdvar = LED3_ON; // debug
524 4 }
525 3 else
526 3 { // EP2EF=0 when FIFO "not" empty, host sent pkt.
527 4 EP2GPIFTCH = EP2BCH; // setup transaction count
528 4 EP2GPIFTCL = EP2BCL; // set EP2GPIFTC = EP2BC
529 4 EP2BCL = 0x00; // AUTOOUT=0, so "pass-on" pkt. to master (GPIF)
530 4 // once master xfr's OUT pkt, it "auto" (re)arms
531 4 // trigger FIFO write transaction(s), using SFR
532 4 *EP0BUF = 0xAB;
533 4 }
534 3 EP0BCH = 0;
535 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
536 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
537 3 BLINK_LED();
538 3 break;
539 3 }
540 2 case VX_AC:
541 2 { // manually commit IN data to host...
542 3 // GPIF needs to still be pointing to EP8, last FIFO accessed
543 3 if( EP2468STAT & 0x80 )
544 3 { // EP8F=1 when buffer is not available
545 4 *EP0BUF = 0x00; // buffer wasn't available
546 4 ledX_rdvar = LED3_ON; // debug
547 4 }
548 3 else
549 3 { // EP8F=0 when buffer is available
550 4 INPKTEND = 0x08; // 8051 commits pkt by writing #8 to INPKTEND
551 4 *EP0BUF = 0xAC;
C51 COMPILER V7.00 GPIFBURST8A 05/20/2003 15:33:07 PAGE 10
552 4 ledX_rdvar = LED3_OFF; // debug
553 4 }
554 3 EP0BCH = 0;
555 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
556 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
557 3 BLINK_LED();
558 3 break;
559 3 }
560 2 case VX_AD:
561 2 { // setup GPIF FIFO Reads w/TC=8
562 3 *EP0BUF = 0xAD;
563 3 EP8GPIFTCH = 0x00; // setup transaction count
564 3 EP8GPIFTCL = 0x08; // EP8GPIFTC = 8
565 3 EP0BCH = 0;
566 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
567 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
568 3 BLINK_LED();
569 3 break;
570 3 }
571 2 case VX_AE:
572 2 { // get status of GPIF
573 3 *EP0BUF = GPIFTRIG; // return status of GPIFDONE bit
574 3 EP0BCH = 0;
575 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
576 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
577 3 BLINK_LED();
578 3 break;
579 3 }
580 2 case VX_AF:
581 2 {
582 3 *EP0BUF = 0xAF; // return status of GPIFDONE bit
583 3 EP8BCH = 0x00; // Commit one zerolen IN pkt
584 3 EP8BCL = 0x00;
585 3 EP0BCH = 0;
586 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
587 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
588 3 BLINK_LED();
589 3 break;
590 3 }
591 2 case VX_B1:
592 2 { // examine flags...
593 3 *EP0BUF = EP8FIFOFLGS;
594 3 EP0BCH = 0;
595 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
596 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
597 3 BLINK_LED();
598 3 break;
599 3 }
600 2 case VX_B2:
601 2 { // examine flags...
602 3 *EP0BUF = EP2468STAT;
603 3 EP0BCH = 0;
604 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
605 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
606 3 BLINK_LED();
607 3 break;
608 3 }
609 2 case VX_B3:
610 2 { // examine flags...
611 3 *EP0BUF = EP68FIFOFLGS;
612 3 EP0BCH = 0;
613 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
C51 COMPILER V7.00 GPIFBURST8A 05/20/2003 15:33:07 PAGE 11
614 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
615 3 BLINK_LED();
616 3 break;
617 3 }
618 2 case VX_B4:
619 2 { // examine bc...
620 3 *EP0BUF = EP8BCH;
621 3 EP0BCH = 0;
622 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
623 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
624 3 BLINK_LED();
625 3 break;
626 3 }
627 2 case VX_B5:
628 2 { // examine bc...
629 3 *EP0BUF = EP8BCL;
630 3 EP0BCH = 0;
631 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
632 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
633 3 BLINK_LED();
634 3 break;
635 3 }
636 2 case VX_B6:
637 2 { // examine bc...
638 3 *EP0BUF = EP8FIFOBCH;
639 3 EP0BCH = 0;
640 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
641 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
642 3 BLINK_LED();
643 3 break;
644 3 }
645 2 case VX_B7:
646 2 { // examine bc...
647 3 *EP0BUF = EP8FIFOBCL;
648 3 EP0BCH = 0;
649 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
650 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
651 3 BLINK_LED();
652 3 break;
653 3 }
654 2 case VX_C1:
655 2 { // examine flags...
656 3 *EP0BUF = EP2FIFOFLGS;
657 3 EP0BCH = 0;
658 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
659 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
660 3 BLINK_LED();
661 3 break;
662 3 }
663 2 case VX_C2:
664 2 { // examine flags...
665 3 *EP0BUF = EP2468STAT;
666 3 EP0BCH = 0;
667 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
668 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
669 3 BLINK_LED();
670 3 break;
671 3 }
672 2 case VX_C3:
673 2 { // examine flags...
674 3 *EP0BUF = EP24FIFOFLGS;
675 3 EP0BCH = 0;
C51 COMPILER V7.00 GPIFBURST8A 05/20/2003 15:33:07 PAGE 12
676 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
677 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
678 3 BLINK_LED();
679 3 break;
680 3 }
681 2 case VX_C4:
682 2 { // examine bc...
683 3 *EP0BUF = EP2BCH;
684 3 EP0BCH = 0;
685 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
686 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
687 3 BLINK_LED();
688 3 break;
689 3 }
690 2 case VX_C5:
691 2 { // examine bc...
692 3 *EP0BUF = EP2BCL;
693 3 EP0BCH = 0;
694 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
695 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
696 3 BLINK_LED();
697 3 break;
698 3 }
699 2 case VX_C6:
700 2 { // examine bc...
701 3 *EP0BUF = EP2FIFOBCH;
702 3 EP0BCH = 0;
703 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
704 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
705 3 BLINK_LED();
706 3 break;
707 3 }
708 2 case VX_C7:
709 2 { // examine bc...
710 3 *EP0BUF = EP2FIFOBCL;
711 3 EP0BCH = 0;
712 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
713 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
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