📄 bwmeter.lst
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E672 +1 152 PORTECFG XDATA 0xE672; // I/O PORTE Alternate Configuration
E678 +1 153 I2CS XDATA 0xE678; // Control & Status
E679 +1 154 I2DAT XDATA 0xE679; // Data
E67A +1 155 I2CTL XDATA 0xE67A; // I2C Control
E67B +1 156 XAUTODAT1 XDATA 0xE67B; // Autoptr1 MOVX access
E67C +1 157 XAUTODAT2 XDATA 0xE67C; // Autoptr2 MOVX access
+1 158
+1 159
+1 160
E680 +1 161 USBCS XDATA 0xE680; // USB Control & Status
E681 +1 162 SUSPEND XDATA 0xE681; // Put chip into suspend
E682 +1 163 WAKEUPCS XDATA 0xE682; // Wakeup source and polarity
E683 +1 164 TOGCTL XDATA 0xE683; // Toggle Control
E684 +1 165 USBFRAMEH XDATA 0xE684; // USB Frame count H
E685 +1 166 USBFRAMEL XDATA 0xE685; // USB Frame count L
E686 +1 167 MICROFRAME XDATA 0xE686; // Microframe count, 0-7
E687 +1 168 FNADDR XDATA 0xE687; // USB Function address
+1 169
+1 170
+1 171
E68A +1 172 EP0BCH XDATA 0xE68A; // Endpoint 0 Byte Count H
E68B +1 173 EP0BCL XDATA 0xE68B; // Endpoint 0 Byte Count L
E68D +1 174 EP1OUTBC XDATA 0xE68D; // Endpoint 1 OUT Byte Count
E68F +1 175 EP1INBC XDATA 0xE68F; // Endpoint 1 IN Byte Count
A51 MACRO ASSEMBLER BWMETER 06/05/2002 14:07:37 PAGE 4
E690 +1 176 EP2BCH XDATA 0xE690; // Endpoint 2 Byte Count H
E691 +1 177 EP2BCL XDATA 0xE691; // Endpoint 2 Byte Count L
E694 +1 178 EP4BCH XDATA 0xE694; // Endpoint 4 Byte Count H
E695 +1 179 EP4BCL XDATA 0xE695; // Endpoint 4 Byte Count L
E698 +1 180 EP6BCH XDATA 0xE698; // Endpoint 6 Byte Count H
E699 +1 181 EP6BCL XDATA 0xE699; // Endpoint 6 Byte Count L
E69C +1 182 EP8BCH XDATA 0xE69C; // Endpoint 8 Byte Count H
E69D +1 183 EP8BCL XDATA 0xE69D; // Endpoint 8 Byte Count L
E6A0 +1 184 EP0CS XDATA 0xE6A0; // Endpoint Control and Status
E6A1 +1 185 EP1OUTCS XDATA 0xE6A1; // Endpoint 1 OUT Control and Status
E6A2 +1 186 EP1INCS XDATA 0xE6A2; // Endpoint 1 IN Control and Status
E6A3 +1 187 EP2CS XDATA 0xE6A3; // Endpoint 2 Control and Status
E6A4 +1 188 EP4CS XDATA 0xE6A4; // Endpoint 4 Control and Status
E6A5 +1 189 EP6CS XDATA 0xE6A5; // Endpoint 6 Control and Status
E6A6 +1 190 EP8CS XDATA 0xE6A6; // Endpoint 8 Control and Status
E6A7 +1 191 EP2FIFOFLGS XDATA 0xE6A7; // Endpoint 2 Flags
E6A8 +1 192 EP4FIFOFLGS XDATA 0xE6A8; // Endpoint 4 Flags
E6A9 +1 193 EP6FIFOFLGS XDATA 0xE6A9; // Endpoint 6 Flags
E6AA +1 194 EP8FIFOFLGS XDATA 0xE6AA; // Endpoint 8 Flags
E6AB +1 195 EP2FIFOBCH XDATA 0xE6AB; // EP2 FIFO total byte count H
E6AC +1 196 EP2FIFOBCL XDATA 0xE6AC; // EP2 FIFO total byte count L
E6AD +1 197 EP4FIFOBCH XDATA 0xE6AD; // EP4 FIFO total byte count H
E6AE +1 198 EP4FIFOBCL XDATA 0xE6AE; // EP4 FIFO total byte count L
E6AF +1 199 EP6FIFOBCH XDATA 0xE6AF; // EP6 FIFO total byte count H
E6B0 +1 200 EP6FIFOBCL XDATA 0xE6B0; // EP6 FIFO total byte count L
E6B1 +1 201 EP8FIFOBCH XDATA 0xE6B1; // EP8 FIFO total byte count H
E6B2 +1 202 EP8FIFOBCL XDATA 0xE6B2; // EP8 FIFO total byte count L
E6B3 +1 203 SUDPTRH XDATA 0xE6B3; // Setup Data Pointer high address byte
E6B4 +1 204 SUDPTRL XDATA 0xE6B4; // Setup Data Pointer low address byte
E6B5 +1 205 SUDPTRCTL XDATA 0xE6B5; // Setup Data Pointer Auto Mode
E6B8 +1 206 SETUPDAT XDATA 0xE6B8; // 8 bytes of SETUP data
+1 207
+1 208
+1 209
E6C0 +1 210 GPIFWFSELECT XDATA 0xE6C0; // Waveform Selector
E6C1 +1 211 GPIFIDLECS XDATA 0xE6C1; // GPIF Done, GPIF IDLE drive mode
E6C2 +1 212 GPIFIDLECTL XDATA 0xE6C2; // Inactive Bus, CTL states
E6C3 +1 213 GPIFCTLCFG XDATA 0xE6C3; // CTL OUT pin drive
E6C4 +1 214 GPIFADRH XDATA 0xE6C4; // GPIF Address H
E6C5 +1 215 GPIFADRL XDATA 0xE6C5; // GPIF Address L
E6D0 +1 216 EP2GPIFTCH XDATA 0xE6D0; // EP2 GPIF Transaction Count High
E6D1 +1 217 EP2GPIFTCL XDATA 0xE6D1; // EP2 GPIF Transaction Count Low
E6D2 +1 218 EP2GPIFFLGSEL XDATA 0xE6D2; // EP2 GPIF Flag select
E6D3 +1 219 EP2GPIFPFSTOP XDATA 0xE6D3; // Stop GPIF EP2 transaction on prog. flag
E6D4 +1 220 EP2GPIFTRIG XDATA 0xE6D4; // EP2 FIFO Trigger
E6D8 +1 221 EP4GPIFTCH XDATA 0xE6D8; // EP4 GPIF Transaction Count High
E6D9 +1 222 EP4GPIFTCL XDATA 0xE6D9; // EP4 GPIF Transactionr Count Low
E6DA +1 223 EP4GPIFFLGSEL XDATA 0xE6DA; // EP4 GPIF Flag select
E6DB +1 224 EP4GPIFPFSTOP XDATA 0xE6DB; // Stop GPIF EP4 transaction on prog. flag
E6DC +1 225 EP4GPIFTRIG XDATA 0xE6DC; // EP4 FIFO Trigger
E6E0 +1 226 EP6GPIFTCH XDATA 0xE6E0; // EP6 GPIF Transaction Count High
E6E1 +1 227 EP6GPIFTCL XDATA 0xE6E1; // EP6 GPIF Transaction Count Low
E6E2 +1 228 EP6GPIFFLGSEL XDATA 0xE6E2; // EP6 GPIF Flag select
E6E3 +1 229 EP6GPIFPFSTOP XDATA 0xE6E3; // Stop GPIF EP6 transaction on prog. flag
E6E4 +1 230 EP6GPIFTRIG XDATA 0xE6E4; // EP6 FIFO Trigger
E6E8 +1 231 EP8GPIFTCH XDATA 0xE6E8; // EP8 GPIF Transaction Count High
E6E9 +1 232 EP8GPIFTCL XDATA 0xE6E9; // EP8GPIF Transaction Count Low
E6EA +1 233 EP8GPIFFLGSEL XDATA 0xE6EA; // EP8 GPIF Flag select
E6EB +1 234 EP8GPIFPFSTOP XDATA 0xE6EB; // Stop GPIF EP8 transaction on prog. flag
E6EC +1 235 EP8GPIFTRIG XDATA 0xE6EC; // EP8 FIFO Trigger
E6F0 +1 236 XGPIFSGLDATH XDATA 0xE6F0; // GPIF Data H (16-bit mode only)
E6F1 +1 237 XGPIFSGLDATLX XDATA 0xE6F1; // Read/Write GPIF Data L & trigger transac
E6F2 +1 238 XGPIFSGLDATLNOX XDATA 0xE6F2; // Read GPIF Data L, no transac trigger
E6F3 +1 239 GPIFREADYCFG XDATA 0xE6F3; // Internal RDY,Sync/Async, RDY5CFG
E6F4 +1 240 GPIFREADYSTAT XDATA 0xE6F4; // RDY pin states
E6F5 +1 241 GPIFABORT XDATA 0xE6F5; // Abort GPIF cycles
A51 MACRO ASSEMBLER BWMETER 06/05/2002 14:07:37 PAGE 5
+1 242
+1 243
+1 244
E6C6 +1 245 FLOWSTATE XDATA 0xE6C6; //Defines GPIF flow state
E6C7 +1 246 FLOWLOGIC XDATA 0xE6C7; //Defines flow/hold decision criteria
E6C8 +1 247 FLOWEQ0CTL XDATA 0xE6C8; //CTL states during active flow state
E6C9 +1 248 FLOWEQ1CTL XDATA 0xE6C9; //CTL states during hold flow state
E6CB +1 249 FLOWSTB XDATA 0xE6CB; //CTL/RDY Signal to use as master data stro
be
E6CC +1 250 FLOWEDGE XDATA 0xE6CC; //Defines active master strobe edge
E6CD +1 251 FLOWSTBHPERIOD XDATA 0xE6CD; //Half Period of output master strobe
E60C +1 252 GPIFHOLDAMOUNT XDATA 0xE60C; //Data delay shift
E67D +1 253 UDMACRCH XDATA 0xE67D; //CRC Upper byte
E67E +1 254 UDMACRCL XDATA 0xE67E; //CRC Lower byte
E67F +1 255 UDMACRCQUAL XDATA 0xE67F; //UDMA In only, host terminated use only
+1 256
+1 257
+1 258
+1 259
E6F8 +1 260 DBUG XDATA 0xE6F8; // Debug
E6F9 +1 261 TESTCFG XDATA 0xE6F9; // Test configuration
E6FA +1 262 USBTEST XDATA 0xE6FA; // USB Test Modes
E6FB +1 263 CT1 XDATA 0xE6FB; // Chirp Test--Override
E6FC +1 264 CT2 XDATA 0xE6FC; // Chirp Test--FSM
E6FD +1 265 CT3 XDATA 0xE6FD; // Chirp Test--Control Signals
E6FE +1 266 CT4 XDATA 0xE6FE; // Chirp Test--Inputs
+1 267
+1 268
+1 269
E740 +1 270 EP0BUF XDATA 0xE740; // EP0 IN-OUT buffer
E780 +1 271 EP10UTBUF XDATA 0xE780; // EP1-OUT buffer
E7C0 +1 272 EP1INBUF XDATA 0xE7C0; // EP1-IN buffer
F000 +1 273 EP2FIFOBUF XDATA 0xF000; // 512/1024-byte EP2 buffer (IN or OUT)
F400 +1 274 EP4FIFOBUF XDATA 0xF400; // 512 byte EP4 buffer (IN or OUT)
F800 +1 275 EP6FIFOBUF XDATA 0xF800; // 512/1024-byte EP6 buffer (IN or OUT)
FC00 +1 276 EP8FIFOBUF XDATA 0xFC00; // 512 byte EP8 buffer (IN or OUT)
+1 277
+1 278 ;/*-----------------------------------------------------------------------------
+1 279 ; Special Function Registers (SFRs)
+1 280 ; The byte registers and bits defined in the following list are based
+1 281 ; on the Synopsis definition of the 8051 Special Function Registers for EZ-USB.
+1 282 ; If you modify the register definitions below, please regenerate the file
+1 283 ; "ezregs.inc" which includes the same basic information for assembly inclusion.
+1 284 ;-----------------------------------------------------------------------------*/
+1 285
+1 286
+1 287
0080 +1 288 IOA DATA 080H;
0081 +1 289 SP DATA 081H;
0082 +1 290 DPL DATA 082H;
0083 +1 291 DPH DATA 083H;
0084 +1 292 DPL1 DATA 084H;
0085 +1 293 DPH1 DATA 085H;
0086 +1 294 DPS DATA 086H;
+1 295 ; DPS
0086 +1 296 SEL BIT 086H+0H;
0087 +1 297 PCON DATA 087H; ; PCON
+1 298 ;IDLE BIT 087H+0H;
+1 299 ;STOP BIT 087H+1H;
+1 300 ;GF0 BIT 087H+2H;
+1 301 ;GF1 BIT 087H+3H;
+1 302 ;SMOD0 BIT 087H+7H;
0088 +1 303 TCON DATA 088H;
+1 304 ; TCON
0088 +1 305 IT0 BIT 088H+0H;
0089 +1 306 IE0 BIT 088H+1H;
A51 MACRO ASSEMBLER BWMETER 06/05/2002 14:07:37 PAGE 6
008A +1 307 IT1 BIT 088H+2H;
008B +1 308 IE1 BIT 088H+3H;
008C +1 309 TR0 BIT 088H+4H;
008D +1 310 TF0 BIT 088H+5H;
008E +1 311 TR1 BIT 088H+6H;
008F +1 312 TF1 BIT 088H+7H;
0089 +1 313 TMOD DATA 089H;
+1 314 ; TMOD
+1 315 ;M00 BIT 089H+0H;
+1 316 ;M10 BIT 089H+1H;
+1 317 ;CT0 BIT 089H+2H;
+1 318 ;GATE0 BIT 089H+3H;
+1 319 ;M01 BIT 089H+4H;
+1 320 ;M11 BIT 089H+5H;
+1 321 ;CT1 BIT 089H+6H;
+1 322 ;GATE1 BIT 089H+7H;
008A +1 323 TL0 DATA 08AH;
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