📄 int.s
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;/* */
;/* HISTORY */
;/* */
;/* NAME DATE REMARKS */
;/* */
;/* W. Lamie 07-15-1993 Created initial version 1.0 */
;/* D. Lamie 07-15-1993 Verified version 1.0 */
;/* */
;/*************************************************************************/
XDEF _INT_Retrieve_Shell
_INT_Retrieve_Shell:
;VOID *INT_Retrieve_Shell(INT vector)
;{
;
; /* Return the LISR Shell interrupt routine. */
; return(INT_Vectors[vector]);
;
LEA _INT_Vectors,A0 ; Build address to default ISRs
MOVE.L 4(A7),D1 ; Pickup the vector number
ASL.L #2,D1 ; Multiply by 4
MOVE.L (A0,D1.W),D0 ; Pickup the default ISR
RTS ; Return to caller
;}
;
;
;/* The following area contains the default interrupt vector processing for
; each interrupt. Note: Nothing else can be placed between the
; INT_Start_ISRs label and the INT_End_ISRs label. */
;
XDEF _INT_Start_ISRs
_INT_Start_ISRs:
;
;
_INT_Bus_Error: ; Bus Error 2
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Address_Error: ; Address Error 3
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Illegal_Instruction: ; Illegal Instruction 4
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Zero_Divide: ; Divide by zero 5
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Chk_Chk2: ; CHK and CHK2 instructions 6
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_TrapV: ; TRAPV instruction 7
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Privilege: ; Privilege violation 8
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Trace: ; Trace 9
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Emul_A: ; Emulate A 10
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Emul_B: ; Emulate B 11
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Hdw_Breakpoint: ; Hardware breakpoint 12
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Coprocessor_Violate: ; Coprocessor violation 13
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Format_Error: ; Format error 14
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Uninitialized_Int: ; Uninitialized interrupt 15
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Reserved_0: ; Reserved 0 16
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Reserved_1: ; Reserved 1 17
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Reserved_2: ; Reserved 2 18
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Reserved_3: ; Reserved 3 19
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Reserved_4: ; Reserved 4 20
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Reserved_5: ; Reserved 5 21
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Reserved_6: ; Reserved 6 22
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Reserved_7: ; Reserved 7 23
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Spurious: ; Spurious interrupt 24
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Level_1_Auto: ; Level 1 Autovector 25
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Level_2_Auto: ; Level 2 Autovector 26
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Level_3_Auto: ; Level 3 Autovector 27
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Level_4_Auto: ; Level 4 Autovector 28
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Level_5_Auto: ; Level 5 Autovector 29
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Level_6_Auto: ; Level 6 Autovector 30
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Level_7_Auto: ; Level 7 Autovector 31
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Trap_0: ; Trap 0 32
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Trap_1: ; Trap 1 33
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Trap_2: ; Trap 2 34
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Trap_3: ; Trap 3 35
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Trap_4: ; Trap 4 36
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Trap_5: ; Trap 5 37
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Trap_6: ; Trap 6 38
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Trap_7: ; Trap 7 39
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Trap_8: ; Trap 8 40
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Trap_9: ; Trap 9 41
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Trap_10: ; Trap 10 42
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Trap_11: ; Trap 11 43
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Trap_12: ; Trap 12 44
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Trap_13: ; Trap 13 45
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Trap_14: ; Trap 14 46
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Trap_15: ; Trap 15 47
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Cop_Reserved_0: ; Coprocessor Reserved 0 48
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Cop_Reserved_1: ; Coprocessor Reserved 1 49
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Cop_Reserved_2: ; Coprocessor Reserved 2 50
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Cop_Reserved_3: ; Coprocessor Reserved 3 51
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Cop_Reserved_4: ; Coprocessor Reserved 4 52
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Cop_Reserved_5: ; Coprocessor Reserved 5 53
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Cop_Reserved_6: ; Coprocessor Reserved 6 54
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Cop_Reserved_7: ; Coprocessor Reserved 7 55
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Cop_Reserved_8: ; Coprocessor Reserved 8 56
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Cop_Reserved_9: ; Coprocessor Reserved 9 57
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Cop_Reserved_10: ; Coprocessor Reserved 10 58
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Reserved_8: ; Reserved 8 59
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Reserved_9: ; Reserved 9 60
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Reserved_10: ; Reserved 10 61
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Reserved_11: ; Reserved 11: 62
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_Reserved_12: ; Reserved 12 63
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_User_0: ; User Interrupt 0 64
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_User_1: ; User Interrupt 1 65
BSR.W _INT_Interrupt_Shell ; Branch to interrupt shell
;
_INT_User_2: ; User Interrupt 2 66
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