mc68332.h

nucleus 的以太网协议栈

******************************************************************************
*									     *
*			   MOTOROLA 68332 DEFINITIONS			     *
*									     *
******************************************************************************
*   NOTE:  All values are offsets from either $7FF000 or $FFF000.	     *
*   The base address is determined by the modmap bit in SIM_MCR.	     *
*   It should be noted that the modmap bit is a write-once bit.  After a     *
*   reset, it is 1 (indicating $FFF000).  The first write to the SIM_MCR     *
*   register will permanently set the modmap bit.			     *
******************************************************************************
#ifndef __MC68332__
#define __MC68332__

#define _arg1	%+4(A7)
#define _arg2	%+8(A7)
#define _arg3	%+12(A7)
#define _arg4	%+16(A7)

;Constant for boolean
TRUE		=1
FALSE		=0
true            =1
false           =0

********************************* CONFIGURATION REGISTERS ********************
SIM_MCR:	equ	$A00	; Module Configuration			(word)
SIM_SIMTR:	equ	$A02	; Module Test Register			(word)

********************************* CLOCK **************************************
SIM_SYNCR:	equ	$A04	; Clock Synthesizer Control		(word)
SIM_RSR:	equ	$A07	; Reset Status Register			(byte)

********************************* EBI ****************************************
SIM_SIMTRE:	equ	$A08	; Module Test E				(word)
SIM_PORTE:	equ	$A11	; Port E Data				(byte)
SIM_PORTE2:	equ	$A13	; Port E Data (same as SIM_PORTE)	(byte)
SIM_DDRE:	equ	$A15	; Port E Data Direction			(byte)
SIM_PEPAR:	equ	$A17	; Port E Pin Assignment			(byte)
SIM_PORTF:	equ	$A19	; Port F Data				(byte)
SIM_PORTF2:	equ	$A1B	; Port F Data (same as SIM_PORTF)	(byte)
SIM_DDRF:	equ	$A1D	; Port F Data Direction			(byte)
SIM_PFPAR:	equ	$A1F	; Port F Pin Assignment			(byte)

********************************* SYSTEM PROTECTION **************************
SIM_SYPCR:	equ	$A21	; System Protection Control		(byte)
SIM_PICR:	equ	$A22	; Periodic Interrupt Control		(word)
SIM_PITR:	equ	$A24	; Periodic Interrupt Timing		(word)
SIM_SWSR:	equ	$A27	; Software Service			(byte)

********************************* TEST ***************************************
SIM_TSTMSRA:	equ	$A30	; Test Module Master Shift A		(word)
SIM_TSTMSRB:	equ	$A32	; Test Module Master Shift B		(word)
SIM_TSTSC:	equ	$A34	; TRest Module Shift Count		(word)
SIM_TSTRC:	equ	$A36	; Test Module Repetition Counter	(word)
SIM_CREG:	equ	$A38	; Test Module Control			(word)
SIM_DREG:	equ	$A3A	; Test Module Distributed Register	(word)

********************************* CHIP SELECT ********************************
SIM_PORTC:	equ	$A41	; Chip-Select Pin Data Register		(byte)
SIM_CSPAR0:	equ	$A44	; Chip-select Pin Assignment		(word)
SIM_CSPAR1:	equ	$A46	; Chip-select Pin Assignment		(word)
SIM_CSBARBT:	equ	$A48	; Chip-select Base Boot			(word)
SIM_CSORBT:	equ	$A4A	; Chip-select Option Boot		(word)
SIM_CSBAR0:	equ	$A4C	; Chip-select Base   #0			(word)
SIM_CSOR0:	equ	$A4E	; Chip-select Option  0			(word)
SIM_CSBAR1:	equ	$A50	; Chip-select Base   #1			(word)
SIM_CSOR1:	equ	$A52	; Chip-select Option  1			(word)
SIM_CSBAR2:	equ	$A54	; Chip-select Base   #2			(word)
SIM_CSOR2:	equ	$A56	; Chip-select Option  2			(word)
SIM_CSBAR3:	equ	$A58	; Chip-select Base   #3			(word)
SIM_CSOR3:	equ	$A5A	; Chip-select Option  3			(word)
SIM_CSBAR4:	equ	$A5C	; Chip-select Base   #4			(word)
SIM_CSOR4:	equ	$A5E	; Chip-select Option  4			(word)
SIM_CSBAR5:	equ	$A60	; Chip-select Base   #5			(word)
SIM_CSOR5:	equ	$A62	; Chip-select Option  5			(word)
SIM_CSBAR6:	equ	$A64	; Chip-select Base   #6			(word)
SIM_CSOR6:	equ	$A66	; Chip-select Option  6			(word)
SIM_CSBAR7:	equ	$A68	; Chip-select Base   #7			(word)
SIM_CSOR7:	equ	$A6A	; Chip-select Option  7			(word)
SIM_CSBAR8:	equ	$A6C	; Chip-select Base   #8			(word)
SIM_CSOR8:	equ	$A6E	; Chip-select Option  8			(word)
SIM_CSBAR9:	equ	$A70	; Chip-select Base   #9			(word)
SIM_CSOR9:	equ	$A72	; Chip-select Option  9			(word)
SIM_CSBAR10:	equ	$A74	; Chip-select Base   #10		(word)
SIM_CSOR10:	equ	$A76	; Chip-select Option  10		(word)

********************************* RAM MODULE *********************************
RAM_MCR:	equ	$B00	; Module Configuration Register		(word)
RAM_TST:	equ	$B02	; Test Register				(word)
RAM_BAR:	equ	$B04	; Base Address/Status Register		(word)

********************************* QUEUED SERIAL MODULE ***********************
QSM_QMCR:	equ	$C00	; QSM Configuration Register		(word)
QSM_QTEST:	equ	$C02	; QSM Test Register			(word)
QSM_QILR:	equ	$C04	; QSM Interrupt Level Register		(byte)
QSM_QIVR:	equ	$C05	; QSM Interrupt Vector Register		(byte)

QSM_SCCR0:	equ	$C08	; SCI Control Register 0		(word)
QSM_SCCR1:	equ	$C0A	; SCI Control Register 1		(word)
QSM_SCSR:	equ	$C0C	; SCI Status Register			(word)
QSM_SCDR:	equ	$C0E	; SCI Data Register			(word)

QSM_QPDR:	equ	$C15	; QSM Port Data Register		(byte)
QSM_QPAR:	equ	$C16	; QSM Pin Assignment Register		(byte)
QSM_QDDR:	equ	$C17	; QSM Data Direction Register		(byte)

QSM_SPCR0:	equ	$C18	; QSPI Control Register 0		(word)
QSM_SPCR1:	equ	$C1A	; QSPI Control Register 1		(word)
QSM_SPCR2:	equ	$C1C	; QSPI Control Register 2		(word)
QSM_SPCR3:	equ	$C1E	; QSPI Control Register 3		(byte)
QSM_SPSR:	equ	$C1F	; QSPI Status Register			(byte)
QSM_SPIRD:	equ	$D00	; QSPI RECEIVE DATA	       (16-word queue)
QSM_SPITD:	equ	$D20	; QSPI TRANSMIT DATA	       (16-word queue)
QSM_SPICC:	equ	$D40	; QSPI COMMAND CONTROL	       (16-byte queue)

********************************* TIME PROCESSOR UNIT ************************
TPU_TMCR:	equ	$E00	; Module Configuration	                (word)
TPU_TTCR:	equ	$E02	; Test Configuration	                (word)
TPU_DSCR:	equ	$E04	; Development Support Control Register	(word)
TPU_DSSR:	equ	$E06	; Development Support Status Register	(word)
TPU_TICR:	equ	$E08	; Interrupt Configuration	        (word)
TPU_CIER:	equ	$E0A	; Interrupt Enable			(word)
TPU_CFSR0:	equ	$E0C	; Channel Function Select #0	        (word)
TPU_CFSR1:	equ	$E0E	; Channel Function Select #1	        (word)
TPU_CFSR2:	equ	$E10	; Channel Function Select #2	        (word)
TPU_CFSR3:	equ	$E12	; Channel Function Select #3	        (word)
TPU_HSQR0:	equ	$E14	; Host Sequence #0			(word)
TPU_HSQR1:	equ	$E16	; Host Sequence #1			(word)
TPU_HSRR0:	equ	$E18	; Host Service Request #0	        (word)
TPU_HSRR1:	equ	$E1A	; Host Service Request #1	        (word)
TPU_CPR0:	equ	$E1C	; Channel Priority #0		        (word)
TPU_CPR1:	equ	$E1E	; Channel Priority #1		        (word)
TPU_CISR:	equ	$E20	; Interrupt Status Register	        (word)
TPU_LINK:	equ	$E22	; Link Register				(word)
TPU_SGLR:	equ	$E24	; Service Grant Latch Register		(word)
TPU_DCNR:	equ	$E26	; Decoded Channel Number Register	(word)

TPU_PRAM0:	equ	$F00	; Parameter RAM #0		(6-word array)
TPU_PRAM1:	equ	$F10	; Parameter RAM #1		(6-word array)
TPU_PRAM2:	equ	$F20	; Parameter RAM #2		(6-word array)
TPU_PRAM3:	equ	$F30	; Parameter RAM #3		(6-word array)
TPU_PRAM4:	equ	$F40	; Parameter RAM #4		(6-word array)
TPU_PRAM5:	equ	$F50	; Parameter RAM #5		(6-word array)
TPU_PRAM6:	equ	$F60	; Parameter RAM #6		(6-word array)
TPU_PRAM7:	equ	$F70	; Parameter RAM #7		(6-word array)
TPU_PRAM8:	equ	$F80	; Parameter RAM #8		(6-word array)
TPU_PRAM9:	equ	$F90	; Parameter RAM #9		(6-word array)
TPU_PRAM10:	equ	$FA0	; Parameter RAM #10		(6-word array)
TPU_PRAM11:	equ	$FB0	; Parameter RAM #11		(6-word array)
TPU_PRAM12:	equ	$FC0	; Parameter RAM #12		(6-word array)
TPU_PRAM13:	equ	$FD0	; Parameter RAM #13		(6-word array)
TPU_PRAM14:	equ	$FE0	; Parameter RAM #14		(8-word array)
TPU_PRAM15:	equ	$FF0	; Parameter RAM #15		(8-word array)

#endif