📄 mx1hw.h
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//#define DMA_SAR0 (DMA_CH0_BASE+0x000)#define DMA_DAR0 (DMA_CH0_BASE+0x004)#define DMA_CNTR0 (DMA_CH0_BASE+0x008)#define DMA_CCR0 (DMA_CH0_BASE+0x00C)#define DMA_RSSR0 (DMA_CH0_BASE+0x010)#define DMA_BLR0 (DMA_CH0_BASE+0x014)#define DMA_RTOR0 (DMA_CH0_BASE+0x018)#define DMA_BUCR0 (DMA_CH0_BASE+0x018)//#define DMA_SAR1 (DMA_CH1_BASE+0x000)#define DMA_DAR1 (DMA_CH1_BASE+0x004)#define DMA_CNTR1 (DMA_CH1_BASE+0x008)#define DMA_CCR1 (DMA_CH1_BASE+0x00C)#define DMA_RSSR1 (DMA_CH1_BASE+0x010)#define DMA_BLR1 (DMA_CH1_BASE+0x014)#define DMA_RTOR1 (DMA_CH1_BASE+0x018)#define DMA_BUCR1 (DMA_CH1_BASE+0x018)//#define DMA_SAR2 (DMA_CH2_BASE+0x000)#define DMA_DAR2 (DMA_CH2_BASE+0x004)#define DMA_CNTR2 (DMA_CH2_BASE+0x008)#define DMA_CCR2 (DMA_CH2_BASE+0x00C)#define DMA_RSSR2 (DMA_CH2_BASE+0x010)#define DMA_BLR2 (DMA_CH2_BASE+0x014)#define DMA_RTOR2 (DMA_CH2_BASE+0x018)#define DMA_BUCR2 (DMA_CH2_BASE+0x018)//#define DMA_SAR3 (DMA_CH3_BASE+0x000)#define DMA_DAR3 (DMA_CH3_BASE+0x004)#define DMA_CNTR3 (DMA_CH3_BASE+0x008)#define DMA_CCR3 (DMA_CH3_BASE+0x00C)#define DMA_RSSR3 (DMA_CH3_BASE+0x010)#define DMA_BLR3 (DMA_CH3_BASE+0x014)#define DMA_RTOR3 (DMA_CH3_BASE+0x018)#define DMA_BUCR3 (DMA_CH3_BASE+0x018)//#define DMA_SAR4 (DMA_CH4_BASE+0x000)#define DMA_DAR4 (DMA_CH4_BASE+0x004)#define DMA_CNTR4 (DMA_CH4_BASE+0x008)#define DMA_CCR4 (DMA_CH4_BASE+0x00C)#define DMA_RSSR4 (DMA_CH4_BASE+0x010)#define DMA_BLR4 (DMA_CH4_BASE+0x014)#define DMA_RTOR4 (DMA_CH4_BASE+0x018)#define DMA_BUCR4 (DMA_CH4_BASE+0x018)//#define DMA_SAR5 (DMA_CH5_BASE+0x000)#define DMA_DAR5 (DMA_CH5_BASE+0x004)#define DMA_CNTR5 (DMA_CH5_BASE+0x008)#define DMA_CCR5 (DMA_CH5_BASE+0x00C)#define DMA_RSSR5 (DMA_CH5_BASE+0x010)#define DMA_BLR5 (DMA_CH5_BASE+0x014)#define DMA_RTOR5 (DMA_CH5_BASE+0x018)#define DMA_BUCR5 (DMA_CH5_BASE+0x018)//#define DMA_SAR6 (DMA_CH6_BASE+0x000)#define DMA_DAR6 (DMA_CH6_BASE+0x004)#define DMA_CNTR6 (DMA_CH6_BASE+0x008)#define DMA_CCR6 (DMA_CH6_BASE+0x00C)#define DMA_RSSR6 (DMA_CH6_BASE+0x010)#define DMA_BLR6 (DMA_CH6_BASE+0x014)#define DMA_RTOR6 (DMA_CH6_BASE+0x018)#define DMA_BUCR6 (DMA_CH6_BASE+0x018)//#define DMA_SAR7 (DMA_CH7_BASE+0x000)#define DMA_DAR7 (DMA_CH7_BASE+0x004)#define DMA_CNTR7 (DMA_CH7_BASE+0x008)#define DMA_CCR7 (DMA_CH7_BASE+0x00C)#define DMA_RSSR7 (DMA_CH7_BASE+0x010)#define DMA_BLR7 (DMA_CH7_BASE+0x014)#define DMA_RTOR7 (DMA_CH7_BASE+0x018)#define DMA_BUCR7 (DMA_CH7_BASE+0x018)//#define DMA_SAR8 (DMA_CH8_BASE+0x000)#define DMA_DAR8 (DMA_CH8_BASE+0x004)#define DMA_CNTR8 (DMA_CH8_BASE+0x008)#define DMA_CCR8 (DMA_CH8_BASE+0x00C)#define DMA_RSSR8 (DMA_CH8_BASE+0x010)#define DMA_BLR8 (DMA_CH8_BASE+0x014)#define DMA_RTOR8 (DMA_CH8_BASE+0x018)#define DMA_BUCR8 (DMA_CH8_BASE+0x018)//#define DMA_SAR9 (DMA_CH9_BASE+0x000)#define DMA_DAR9 (DMA_CH9_BASE+0x004)#define DMA_CNTR9 (DMA_CH9_BASE+0x008)#define DMA_CCR9 (DMA_CH9_BASE+0x00C)#define DMA_RSSR9 (DMA_CH9_BASE+0x010)#define DMA_BLR9 (DMA_CH9_BASE+0x014)#define DMA_RTOR9 (DMA_CH9_BASE+0x018)#define DMA_BUCR9 (DMA_CH9_BASE+0x018)//#define DMA_SAR10 (DMA_CH10_BASE+0x000)#define DMA_DAR10 (DMA_CH10_BASE+0x004)#define DMA_CNTR10 (DMA_CH10_BASE+0x008)#define DMA_CCR10 (DMA_CH10_BASE+0x00C)#define DMA_RSSR10 (DMA_CH10_BASE+0x010)#define DMA_BLR10 (DMA_CH10_BASE+0x014)#define DMA_RTOR10 (DMA_CH10_BASE+0x018)#define DMA_BUCR10 (DMA_CH10_BASE+0x018)// #define DMA_TCR (DMA_TST_BASE+0x000)#define DMA_TFIFOA (DMA_TST_BASE+0x004)#define DMA_TDRR (DMA_TST_BASE+0x008)#define DMA_TDIPR (DMA_TST_BASE+0x00C)#define DMA_TFIFOB (DMA_TST_BASE+0x010)// // ;---------------------------------------;// ; DSPA ;// ; $0022_2000 to $0022_2FFF ;// ;---------------------------------------;#define DSPA_BASE_ADDR 0x00222000// #define DSPA_MAC_MOD (DSPA_BASE_ADDR+0x0000)#define DSPA_MAC_CTRL (DSPA_BASE_ADDR+0x0004)#define DSPA_MAC_MULT (DSPA_BASE_ADDR+0x0008)#define DSPA_MAC_ACCU (DSPA_BASE_ADDR+0x000C)#define DSPA_MAC_INTR (DSPA_BASE_ADDR+0x0010)#define DSPA_MAC_INTR_MASK (DSPA_BASE_ADDR+0x0014)#define DSPA_MAC_FIFO (DSPA_BASE_ADDR+0x0018)#define DSPA_MAC_FIFO_STAT (DSPA_BASE_ADDR+0x001C)#define DSPA_MAC_BURST (DSPA_BASE_ADDR+0x0020)#define DSPA_MAC_BIT_SEL (DSPA_BASE_ADDR+0x0024)//#define DSPA_MAC_XBASE (DSPA_BASE_ADDR+0x0200)#define DSPA_MAC_XINDEX (DSPA_BASE_ADDR+0x0204)#define DSPA_MAC_XLENGTH (DSPA_BASE_ADDR+0x0208)#define DSPA_MAC_XMODIFY (DSPA_BASE_ADDR+0x020C)#define DSPA_MAC_XINCR (DSPA_BASE_ADDR+0x0210)#define DSPA_MAC_XCOUNT (DSPA_BASE_ADDR+0x0214)//#define DSPA_MAC_YBASE (DSPA_BASE_ADDR+0x0300)#define DSPA_MAC_YINDEX (DSPA_BASE_ADDR+0x0304)#define DSPA_MAC_YLENGTH (DSPA_BASE_ADDR+0x0308)#define DSPA_MAC_YMODIFY (DSPA_BASE_ADDR+0x030C)#define DSPA_MAC_YINCR (DSPA_BASE_ADDR+0x0310)#define DSPA_MAC_YCOUNT (DSPA_BASE_ADDR+0x0314)//#define DSPA_DCTCTRL (DSPA_BASE_ADDR+0x0400)#define DSPA_DCTVER (DSPA_BASE_ADDR+0x0404)#define DSPA_DCTIRQENA (DSPA_BASE_ADDR+0x0408)#define DSPA_DCTIRQSTAT (DSPA_BASE_ADDR+0x040C)#define DSPA_DCTSRCADD (DSPA_BASE_ADDR+0x0410)#define DSPA_DCTDESADD (DSPA_BASE_ADDR+0x0414)#define DSPA_DCTFIFO (DSPA_BASE_ADDR+0x0500)//// ;---------------------------------------;// ; ESRAM ;// ; $0030_D000 to $0031_FFFF ;// ;---------------------------------------;#define eSRAM_ADDR_BOT 0x00300000 // ; Bottom of eSRAM#define eSRAM_ADDR_TOP 0x00319000 // ; Top of physical eSRAM#define eSRAM_ADDR_LMT 0x003FFFFF // ; Limit of allocated eSRAM#define eSRAM_PHY_SIZE 0x00018000 // ; Physical size of eSRAM (96k)#define eSRAM_ASS_SIZE 0x00100000 // ; Assigned size of eSRAM (1M)#define eSRAM_8K_SIZE 0x00008000 // ; 8k byte size for boundary between RAM1 & RAM2//// ;---------------------------------------;// ; GPIO - PTA ;// ; $0021_C000 to $0021_C0FF ;// ;---------------------------------------;#define PTA_BASE_ADDR 0xF021C000 #define PTA_DDIR PTA_BASE_ADDR #define PTA_OCR1 (PTA_BASE_ADDR+0x04) #define PTA_OCR2 (PTA_BASE_ADDR+0x08) #define PTA_ICONFA1 (PTA_BASE_ADDR+0x0C) #define PTA_ICONFA2 (PTA_BASE_ADDR+0x10) #define PTA_ICONFB1 (PTA_BASE_ADDR+0x14) #define PTA_ICONFB2 (PTA_BASE_ADDR+0x18) #define PTA_DR (PTA_BASE_ADDR+0x1C) #define PTA_GIUS (PTA_BASE_ADDR+0x20) #define PTA_SSR (PTA_BASE_ADDR+0x24) #define PTA_ICR1 (PTA_BASE_ADDR+0x28) #define PTA_ICR2 (PTA_BASE_ADDR+0x2C) #define PTA_IMR (PTA_BASE_ADDR+0x30) #define PTA_ISR (PTA_BASE_ADDR+0x34) #define PTA_GPR (PTA_BASE_ADDR+0x38) #define PTA_SWR (PTA_BASE_ADDR+0x3C) #define PTA_PUEN (PTA_BASE_ADDR+0x40) //// ;---------------------------------------;// ; GPIO - PTB ; // ; $0021_C100 to $0021_C1FF ; // ;---------------------------------------; #define PTB_BASE_ADDR 0xF021C100 #define PTB_DDIR PTB_BASE_ADDR #define PTB_OCR1 (PTB_BASE_ADDR+0x04) #define PTB_OCR2 (PTB_BASE_ADDR+0x08) #define PTB_ICONFA1 (PTB_BASE_ADDR+0x0C) #define PTB_ICONFA2 (PTB_BASE_ADDR+0x10) #define PTB_ICONFB1 (PTB_BASE_ADDR+0x14) #define PTB_ICONFB2 (PTB_BASE_ADDR+0x18) #define PTB_DR (PTB_BASE_ADDR+0x1C) #define PTB_GIUS (PTB_BASE_ADDR+0x20) #define PTB_SSR (PTB_BASE_ADDR+0x24) #define PTB_ICR1 (PTB_BASE_ADDR+0x28) #define PTB_ICR2 (PTB_BASE_ADDR+0x2C) #define PTB_IMR (PTB_BASE_ADDR+0x30) #define PTB_ISR (PTB_BASE_ADDR+0x34) #define PTB_GPR (PTB_BASE_ADDR+0x38) #define PTB_SWR (PTB_BASE_ADDR+0x3C) #define PTB_PUEN (PTB_BASE_ADDR+0x40)// ;---------------------------------------;// ; GPIO - PTC ;// ; $0021_C200 to $0021_C2FF ;// ;---------------------------------------;#define PTC_BASE_ADDR 0x0021C200 #define PTC_DDIR PTC_BASE_ADDR #define PTC_OCR1 (PTC_BASE_ADDR+0x04) #define PTC_OCR2 (PTC_BASE_ADDR+0x08) #define PTC_ICONFA1 (PTC_BASE_ADDR+0x0C) #define PTC_ICONFA2 (PTC_BASE_ADDR+0x10) #define PTC_ICONFB1 (PTC_BASE_ADDR+0x14) #define PTC_ICONFB2 (PTC_BASE_ADDR+0x18) #define PTC_DR (PTC_BASE_ADDR+0x1C) #define PTC_GIUS (PTC_BASE_ADDR+0x20) #define PTC_SSR (PTC_BASE_ADDR+0x24) #define PTC_ICR1 (PTC_BASE_ADDR+0x28) #define PTC_ICR2 (PTC_BASE_ADDR+0x2C) #define PTC_IMR (PTC_BASE_ADDR+0x30) #define PTC_ISR (PTC_BASE_ADDR+0x34) #define PTC_GPR (PTC_BASE_ADDR+0x38) #define PTC_SWR (PTC_BASE_ADDR+0x3C) #define PTC_PUEN (PTC_BASE_ADDR+0x40) // ;---------------------------------------;// ; GPIO - PTD ;// ; $0021_C300 to $0021_C3FF ;// ;---------------------------------------;#define PTD_BASE_ADDR 0x0021C300 #define PTD_DDIR PTD_BASE_ADDR #define PTD_OCR1 (PTD_BASE_ADDR+0x04) #define PTD_OCR2 (PTD_BASE_ADDR+0x08) #define PTD_ICONFA1 (PTD_BASE_ADDR+0x0C) #define PTD_ICONFA2 (PTD_BASE_ADDR+0x10) #define PTD_ICONFB1 (PTD_BASE_ADDR+0x14) #define PTD_ICONFB2 (PTD_BASE_ADDR+0x18) #define PTD_DR (PTD_BASE_ADDR+0x1C) #define PTD_GIUS (PTD_BASE_ADDR+0x20) #define PTD_SSR (PTD_BASE_ADDR+0x24) #define PTD_ICR1 (PTD_BASE_ADDR+0x28) #define PTD_ICR2 (PTD_BASE_ADDR+0x2C) #define PTD_IMR (PTD_BASE_ADDR+0x30) #define PTD_ISR (PTD_BASE_ADDR+0x34) #define PTD_GPR (PTD_BASE_ADDR+0x38) #define PTD_SWR (PTD_BASE_ADDR+0x3C) ⌨️ 快捷键说明
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