target.nr

860最小系统的bsp

    ppc860Timer.c - Timer library for PPC decrementer, CPM timers 2,3,4
    ppc860Sio.o	  - Serial Communications library for SMC UART
    ppc860Intr.c  - Programmable Interrupt Controller Library
    if_cpm.o	  - Ethernet Communication library for SCC
    motCpmEnd.o	  - END-style Ethernet Communication library for SCC
    motFecEnd.o	  - END-style Fast-Ethernet Controller Communication library
		    for MPC860DB daughter-boards with MPC860T microprocessor
    sysMotCpmEnd.c- configuration module for motCpmEnd driver

.PP
The timer driver, ppc860Timer, implements a system clock using the PPC
decrementer timer, an auxiliary clock using CPM timer 2, and a 32-bit
timestamp facilty by cascading CPM timers 3 & 4. The BSP configures SMC1 
as a UART to implement a console device and the CPM SCC1 as an ethernet 
port. The name `cpm' should be specified as the boot device to the boot 
ROMs when booting vxWorks over that interface. To disable the CPM SCC1,
undefine the macro INCLUDE_CPM in the file config.h. Also, undefine the
macro INCLUDE_END if you want to use the non-END-style network driver.
On MPC860DB daughter-boards with MPC860T microprocessor, the Fast 
Ethernet Controller (FEC) makes available fast Ethernet connectivity 
through the use of a MII-compliant physical device and a RJ45 connector.
Support for those board is granted if the macro FADS_860T is defined in 
config.h. In this case, the FEC will be used as the default network 
interface, while the CPM SCC1 will be disabled. However, the user may 
enable either interfaces, and even the configuration where both of them 
are exploited is supported. Each time config.h is edited, new vxWorks
and bootrom images should be built and Flash memory is to be programmed.
If the user wishes to use the FEC as the boot device, the string `motfec' 
should be specified in the boot string.
.PP

.SH "SPECIAL CONSIDERATIONS"
.PP
The DRAM controller setup is only performed by the boot program. VxWorks
doesn't re-initialize the DRAM controller when it is executed.
The DRAM memory controller initialization code can recognize both
the size and type of the DRAM plugged and its access time.
.PP
To increase performance in high operation frequencies, on FADS8xx boards,
the on-board SDRAM bank may be used as the local system memory. However,
the only supported configuration is the one with the clock speed above
32 Mhz., and only for late revisions of the silicon. More to the point,
MPC860T processors with Rev. mask lower than B3 and date code earlier than 
9832, or MPC860EN with Rev. lower than B1 and date code earlier than 9829, 
are not garanteed to work with the same UPM tables (see romInit.s). 
In order to configure the system to initialize the SDRAM, define the macro 
INCLUDE_SDRAM in config.h. Both the SDRAM banks and the regular DRAM SIMM 
are mapped to the lower memory addressing space of the processor, and 
therefore they cannot be used at the same time. If the user wishes to do 
so, this bsp has to be modified.
.PP
This bsp defaults to disable both instruction and data cache when 
the macro EDO_DRAM is defined in config.h. However, Motorola claims
the problem only occurs on early revisions of ADS860 and FADS8xx boards.
To add cache support even when EDO_DRAM is defined, remove unnecessary 
undefine of the cache-related macros in config.h
.PP
Some early revisions of MPC821 and MPC850 lack the ability of supporting
the timestamp driver, since they only feature two internal timers, whereas
the timestamp driver uses timer 3 and timer 4 in cascade mode. On these 
processors, the timestamp library support is not available.
.PP
Support to the second serial channel (SMC) is not available on boards using 
either an MPC823 or an MPC850. In this case, the configuration module for the
serial driver only initializes the first serial channel.
.PP
The module sysMotCpmEnd.c creates the load string for the END-style cpm 
interface. The Ethernet tranceiver on the FADS8xx boards is normally wired
to the SCC1 channel of the Communication Processor Module (CPM). However, 
on FADS823/850 boards, SCC2 is used instead. The module sysMotCpmEnd.c 
dinamically configures the driver to use either the SCC1 or the SCC2 channel 
by reading the BCSR3 register to find out which processor is being used and 
set up the load string accordingly. The user does not need to perform any
other configuration, unless he wants to change default parameters.

.PP
The MPC8xx(F)ADS boards do not have a unique Ethernet hardware
address assigned to each board.  A unique address is absolutely necessary if
the user wishes to connect the board to a network.  Thus, the user
must provide a suitable 6 byte Ethernet address for each board used
on a network.  The address is programmed by changing the sysCpmEnetAddr
character array in the file sysLib.c.  The first three bytes (0x08, 0x00, 0x3e)
are a Motorola-specific prefix that should be kept as-is.  The user must
change the last three bytes from 0x03, 0x02, 0x01 to three unique bytes
(i.e., bytes not used by any other Motorola Ethernet connection on your net).
Check with your system administrator if you do not know this information.
If these bytes need changing (they often will not), a new boot ROM
must be burned, and a new image must be built.
Likewise, the sysFecEnetAddr character array in the file sysLib.c 
must provide a suitable 6 byte Ethernet address for each board where 
the FEC is used. The user must change the last three bytes from 0x03, 0x02,
0x02 to three unique bytes that are not used on any other Motorola 
connection on the user's network. Check with your system administrator 
if you do not know this information. If these bytes need changing (they 
often will not), a new boot ROM must be burned, and a new image must be built.

.PP
The MC68160 EEST part is very sensitive to its input power voltage (VDD).
VDD to the chip must be between 4.75 and 5.25; values outside this
range may diminish functionality.  Therefore, the power supplied to the
target board and the chip should be checked carefully.  Note that there
may be a significant voltage drop between the power supply connectors
and the chip (the fuses and connectors alone cause approximately a
0.1 volts drop).
In order to get the Ethernet device to work properly the processor clock (PLL)
should be at least 24 megahertz. Both the boot program and VxWorks set
the processor clock to 24 megahertz. Configurations with processors running
at a frequency higher than 24 megahertz or lower than 20 megahertz were not
tested. 
.PP
The driver for the FEC exploits the MII Management Interface as described
in the IEEE802.3 standard. In order to do so, it assumes that the 
auto-negotiation function bit MF0 on the on-board dip switch DS1 is in the 
OFF condition. In this configuration, which is also the default one, the 
PHY can advertise its technical abilities and its link may be dynamically 
established in software.  The man page for the FEC driver explains how the 
process to establish a valid physical link for this device may be affected 
by the user settings.  However, if the above MF0 bit is not in the default 
configuration, the driver may fail to initialize the link. Nevertheless, 
the user may write his own media initialization routine and set the function 
pointer _func_motFecPhyInit to the address of this routine. See the man entry 
motFecEnd for more information.

.PP
The FEC, although capable of operating in 100Base-T networks, performs 
poorly under vxWorks. Tests conducted by WRS, on a FADS860 board equipped 
with a MCP860T microprocessor running at 50Mhz bus speed, and regular DRAM 
with 60 nsec access time, in the default configuration (see config.h), 
demonstrated that the attained throughput with TCP/IP applications is 
around 14 Mbit/sec. This goes up to 17 Mbit/sec if the on-board SDRAM is 
used instead. These figures were achieved with data cache turned off. 
This is the only supported configuration by WRS, due to the on-going 
problems with the data cache on the MPC860T processors. Refer to the CPU6 
errata in the document: "MPC860 Family Device Errata Reference" available 
at the above mentioned Motorola web site. The work-around described there 
has not been implemented by WRS, although it is available as a patch. This has
to be linked to the proper arch library if data cache is enabled. The 
lines below describe how to do it. Please contact the WRS's Customer Support 
for more information. Availability of this patch will increase the throughput 
of the FEC in TCP/IP applications to around 28 Mbit/sec.
Please, also note that other device errata are not addressed by this patch, 
and WRS is not responsible for any problem caused by any of them. 

In order to configure VxWorks to link the data cache patch above, add the
following line to the Makefile in target/config/ads860:
.CS
    ADDED_MODULES = dataCachePatch.obj
.CE
Then remove the line undefining USER_D_CACHE_ENABLE from config.h, and rebuild
VxWorks.
.PP

.SS "Known Problems"
VxWorks rom-resident (ROM_RESIDENT flag defined) images do not build for 
this BSP. The same holds true for resident bootroms. In addition, the targets
vxWorks.res_rom_res_low and bootrom_res_high build but do not work. Use 
non-rom-resident images instead.

.SH "SEE ALSO"
.pG "Getting Started, Configuration"