bsc860.h

860最小系统的bsp

/* Copyright 1984-1997 Wind River Systems, Inc. */

/*
*/

/*

*/
#ifndef	INCbsc860h
#define	INCbsc860h

#include "drv/mem/memDev.h"
#include "drv/intrCtl/ppc860Intr.h"

#define BUS	0				/* bus-less board */
#define CPU	PPC860				/* CPU type */

#ifdef  SMC2_SERAIL
#define N_SIO_CHANNELS	 	2		/* No. serial I/O channels */
#else
#define N_SIO_CHANNELS          1
#endif

#undef  BSC860_MPU                            
/*if MPU board ,define it */
#undef  BSC860_V5
/*if V5 board ,define it*/
#undef  BSC860_E1
/*if E1 board, define it*/
#undef  BSC860_NET
/*if NET board , define it */

#ifdef  BSC860_MPU
/*the information about this board */
#endif

#ifdef  BSC860_V5
/*the information about this board */
#endif

#ifdef  BSC860_E1
/*the information about this board */
#endif

#ifdef  BSC860_NET
/*the information about this board */
#endif

#define FREQ_20_MHZ		20000000	/* 20 Mhz */
#define FREQ_25_MHZ		25000000	/* 25 Mhz */
#define FREQ_50_MHZ		50000000	/* 50 Mhz */



/* 
 * SPLL Multiplication Factor: use to set the MF bits of the PLPRCR register.
 * PLPRCR is set by sysHwInit() in sysLib.c. 
 * SPLL_FREQ_REQUESTED and CRISTAL_FREQ are defined in config.h
 */

#define SPLL_MUL_FACTOR	((SPLL_FREQ_REQUESTED / CRISTAL_FREQ) - 1)

/*
 * SPLL Frequency - gives the SPLL real frequency divide by 2
 */

#define SPLL_FREQ	((SPLL_MUL_FACTOR + 1) * CRISTAL_FREQ)

/*
 * Baud Rate Generator Clock - gives the Baud Rate Generator Clock (BRGCLK)
 * Frequency. 
 */

#define BRGCLK_FREQ	(SPLL_FREQ / ( 1 << (2 * BRGCLK_DIV_FACTOR)))

/* 
 * Refresh value - defines the number of BRGCLK period between two 
 * DRAM refresh cycle.
 */

#define REFRESH_VALUE	(BRGCLK_FREQ / DRAM_REFRESH_FREQ)

/* 
 * Periodic Timer A period - value used to set the PTA bits of
 * the Machine A Mode Register (MAMR). This register is used to
 * controle the User_Programmable Machine A (UPM). The UPM is part of
 * the memory controller.
 */

/*#define PTA_VALUE	(( REFRESH_VALUE / 64) != 0 ? (REFRESH_VALUE / 64) : \
			 ((REFRESH_VALUE / 32) != 0 ? (REFRESH_VALUE / 32) : \
			 ((REFRESH_VALUE / 16) != 0 ? (REFRESH_VALUE / 16) : \
			 ((REFRESH_VALUE /  8) != 0 ? (REFRESH_VALUE /  8) : \
			 ((REFRESH_VALUE /  4) != 0 ? (REFRESH_VALUE /  4) : \
			  (REFRESH_VALUE /  2))))))*/

/* 
 * Periodic Timer Prescaler Division Factor - gives the division factor
 * of the Periodic Timer Prescaler (PTP). The PTP is part of the 
 * memory controller. It divide the BRGCLK (Baud Rate Generator Clock) by
 * either 2, 4, 8, 16, 32 or 64 and send this divided clock to the
 * Periodic Timer. 
 * This macro is used to set the DRAM refresh cycle period.
 */

/*#define PTP_DIV_FACTOR	(REFRESH_VALUE / PTA_VALUE)*/

/*
 * PTP Value - translate the Periodic Timer Prescaler Division Factor 
 * to the value to place in the PTP register.
 */

/*#define PTP_VALUE	( PTP_DIV_FACTOR ==  2 ? MPTPR_PTP_DIV2 : \
			 (PTP_DIV_FACTOR ==  4 ? MPTPR_PTP_DIV4 : \
			 (PTP_DIV_FACTOR ==  8 ? MPTPR_PTP_DIV8 : \
			 (PTP_DIV_FACTOR == 16 ? MPTPR_PTP_DIV16 : \
			 (PTP_DIV_FACTOR == 32 ? MPTPR_PTP_DIV32 : \
			  MPTPR_PTP_DIV64)))))*/

/* */

#define TMBCLK_FREQ	CRISTAL_FREQ/4

/* define the decrementer input clock frequency */

#define DEC_CLOCK_FREQ	TMBCLK_FREQ


/* define system clock rate */

#define	SYS_CPU_FREQ	SPLL_FREQ

/* Internal Memory Map base Address */

#define INTERNAL_MEM_MAP_ADDR		0xff000000	
#define INTERNAL_MEM_MAP_SIZE		0x00010000	/* 64 K bytes */

/* size of the on-board SDRAM */

#define SDRAM_SIZE			0x02000000	/* 32 Meg */
#define SDRAM_REFRESH_FREQ		64000		/* 64 Khz */


/* CPU type in the PVR */

#define CPU_TYPE_860			0x0050		/* value for PPC860 */
#define	CPU_REV_A1_MASK_NUM		0x0010		/* revision mask num */

/* Ethernet parameters */
#ifdef  INCLUDE_CPM                                             
                                                                               
/*#define INCLUDE_IF_USR
#define IF_USR_NAME     "cpm"                   
#define IF_USR_ATTACH   cpmattach               
						
#define IF_USR_ARG1     (char *) INTERNAL_MEM_MAP_ADDR + 0x3c00 

#define IF_USR_ARG2     (int) INTERNAL_MEM_MAP_ADDR + 0x0a00    
#define IF_USR_ARG3     (int) IV_SCC1           
#define IF_USR_ARG4     (int) INTERNAL_MEM_MAP_ADDR + 0x2800
						
#define IF_USR_ARG5     (int) INTERNAL_MEM_MAP_ADDR + 0x2900
#define IF_USR_ARG6     (int) 0x20              
#define IF_USR_ARG7     (int) 0x20              
#define IF_USR_ARG8     (int) NONE  */    

#endif
#endif