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1 ;--------------------------------------------------------
2 ; File Created by SDCC : FreeWare ANSI-C Compiler
3 ; Version 2.3.8 Thu Mar 17 22:15:21 2005
4
5 ;--------------------------------------------------------
6 .module file1
7 .optsdcc -mmcs51 --model-small
8
9 ;--------------------------------------------------------
10 ; Public variables in this module
11 ;--------------------------------------------------------
12 .globl _main
13 .globl _delay
14 ;--------------------------------------------------------
15 ; special function registers
16 ;--------------------------------------------------------
0080 17 _P0 = 0x0080
0081 18 _SP = 0x0081
0082 19 _DPL = 0x0082
0083 20 _DPH = 0x0083
0087 21 _PCON = 0x0087
0088 22 _TCON = 0x0088
0089 23 _TMOD = 0x0089
008A 24 _TL0 = 0x008a
008B 25 _TL1 = 0x008b
008C 26 _TH0 = 0x008c
008D 27 _TH1 = 0x008d
0090 28 _P1 = 0x0090
0098 29 _SCON = 0x0098
0099 30 _SBUF = 0x0099
00A0 31 _P2 = 0x00a0
00A8 32 _IE = 0x00a8
00B0 33 _P3 = 0x00b0
00B8 34 _IP = 0x00b8
00D0 35 _PSW = 0x00d0
00E0 36 _ACC = 0x00e0
00F0 37 _B = 0x00f0
38 ;--------------------------------------------------------
39 ; special function bits
40 ;--------------------------------------------------------
0080 41 _P0_0 = 0x0080
0081 42 _P0_1 = 0x0081
0082 43 _P0_2 = 0x0082
0083 44 _P0_3 = 0x0083
0084 45 _P0_4 = 0x0084
0085 46 _P0_5 = 0x0085
0086 47 _P0_6 = 0x0086
0087 48 _P0_7 = 0x0087
0088 49 _IT0 = 0x0088
0089 50 _IE0 = 0x0089
008A 51 _IT1 = 0x008a
008B 52 _IE1 = 0x008b
008C 53 _TR0 = 0x008c
008D 54 _TF0 = 0x008d
008E 55 _TR1 = 0x008e
008F 56 _TF1 = 0x008f
0090 57 _P1_0 = 0x0090
0091 58 _P1_1 = 0x0091
0092 59 _P1_2 = 0x0092
0093 60 _P1_3 = 0x0093
0094 61 _P1_4 = 0x0094
0095 62 _P1_5 = 0x0095
0096 63 _P1_6 = 0x0096
0097 64 _P1_7 = 0x0097
0098 65 _RI = 0x0098
0099 66 _TI = 0x0099
009A 67 _RB8 = 0x009a
009B 68 _TB8 = 0x009b
009C 69 _REN = 0x009c
009D 70 _SM2 = 0x009d
009E 71 _SM1 = 0x009e
009F 72 _SM0 = 0x009f
00A0 73 _P2_0 = 0x00a0
00A1 74 _P2_1 = 0x00a1
00A2 75 _P2_2 = 0x00a2
00A3 76 _P2_3 = 0x00a3
00A4 77 _P2_4 = 0x00a4
00A5 78 _P2_5 = 0x00a5
00A6 79 _P2_6 = 0x00a6
00A7 80 _P2_7 = 0x00a7
00A8 81 _EX0 = 0x00a8
00A9 82 _ET0 = 0x00a9
00AA 83 _EX1 = 0x00aa
00AB 84 _ET1 = 0x00ab
00AC 85 _ES = 0x00ac
00AF 86 _EA = 0x00af
00B0 87 _P3_0 = 0x00b0
00B1 88 _P3_1 = 0x00b1
00B2 89 _P3_2 = 0x00b2
00B3 90 _P3_3 = 0x00b3
00B4 91 _P3_4 = 0x00b4
00B5 92 _P3_5 = 0x00b5
00B6 93 _P3_6 = 0x00b6
00B7 94 _P3_7 = 0x00b7
00B0 95 _RXD = 0x00b0
00B1 96 _TXD = 0x00b1
00B2 97 _INT0 = 0x00b2
00B3 98 _INT1 = 0x00b3
00B4 99 _T0 = 0x00b4
00B5 100 _T1 = 0x00b5
00B6 101 _WR = 0x00b6
00B7 102 _RD = 0x00b7
00B8 103 _PX0 = 0x00b8
00B9 104 _PT0 = 0x00b9
00BA 105 _PX1 = 0x00ba
00BB 106 _PT1 = 0x00bb
00BC 107 _PS = 0x00bc
00D0 108 _P = 0x00d0
00D1 109 _F1 = 0x00d1
00D2 110 _OV = 0x00d2
00D3 111 _RS0 = 0x00d3
00D4 112 _RS1 = 0x00d4
00D5 113 _F0 = 0x00d5
00D6 114 _AC = 0x00d6
00D7 115 _CY = 0x00d7
116 ;--------------------------------------------------------
117 ; overlayable register banks
118 ;--------------------------------------------------------
119 .area REG_BANK_0 (REL,OVR,DATA)
0000 120 .ds 8
121 ;--------------------------------------------------------
122 ; internal ram data
123 ;--------------------------------------------------------
124 .area DSEG (DATA)
125 ;--------------------------------------------------------
126 ; overlayable items in internal ram
127 ;--------------------------------------------------------
128 .area OSEG (OVR,DATA)
129 ;--------------------------------------------------------
130 ; Stack segment in internal ram
131 ;--------------------------------------------------------
132 .area SSEG (DATA)
0008 133 __start__stack:
0008 134 .ds 1
135
136 ;--------------------------------------------------------
137 ; indirectly addressable internal ram data
138 ;--------------------------------------------------------
139 .area ISEG (DATA)
140 ;--------------------------------------------------------
141 ; bit data
142 ;--------------------------------------------------------
143 .area BSEG (BIT)
144 ;--------------------------------------------------------
145 ; external ram data
146 ;--------------------------------------------------------
147 .area XSEG (XDATA)
148 ;--------------------------------------------------------
149 ; external initialized ram data
150 ;--------------------------------------------------------
151 .area XISEG (XDATA)
152 ;--------------------------------------------------------
153 ; interrupt vector
154 ;--------------------------------------------------------
155 .area CSEG (CODE)
0000 156 __interrupt_vect:
0000 02 00 DE 157 ljmp __sdcc_gsinit_startup
0003 32 158 reti
0004 159 .ds 7
000B 32 160 reti
000C 161 .ds 7
0013 32 162 reti
0014 163 .ds 7
001B 32 164 reti
001C 165 .ds 7
0023 32 166 reti
0024 167 .ds 7
002B 32 168 reti
169 ;--------------------------------------------------------
170 ; global & static initialisations
171 ;--------------------------------------------------------
172 .area GSINIT (CODE)
173 .area GSFINAL (CODE)
174 .area GSINIT (CODE)
00DE 175 __sdcc_gsinit_startup:
00DE 75 81 07 176 mov sp,#__start__stack - 1
00E1 12 00 DA 177 lcall __sdcc_external_startup
00E4 E5 82 178 mov a,dpl
00E6 60 03 179 jz __sdcc_init_data
00E8 02 00 2C 180 ljmp __sdcc_program_startup
00EB 181 __sdcc_init_data:
182 ; _mcs51_genXINIT() start
00EB 79 00 183 mov r1,#l_XINIT
00ED E9 184 mov a,r1
00EE 44 00 185 orl a,#(l_XINIT >> 8)
00F0 60 1B 186 jz 00003$
00F2 7A 00 187 mov r2,#((l_XINIT+255) >> 8)
00F4 90 01 26 188 mov dptr,#s_XINIT
00F7 78 00 189 mov r0,#s_XISEG
00F9 75 A0 00 190 mov p2,#(s_XISEG >> 8)
00FC E4 191 00001$: clr a
00FD 93 192 movc a,@a+dptr
00FE F2 193 movx @r0,a
00FF A3 194 inc dptr
0100 08 195 inc r0
0101 B8 00 02 196 cjne r0,#0,00002$
0104 05 A0 197 inc p2
0106 D9 F4 198 00002$: djnz r1,00001$
0108 DA F2 199 djnz r2,00001$
010A 75 A0 FF 200 mov p2,#0xFF
010D 201 00003$:
202 ; _mcs51_genXINIT() end
203 ; _mcs51_genRAMCLEAR() start
010D 78 00 204 mov r0,#l_XSEG
010F E8 205 mov a,r0
0110 44 00 206 orl a,#(l_XSEG >> 8)
0112 60 0C 207 jz 00005$
0114 79 00 208 mov r1,#((l_XSEG + 255) >> 8)
0116 90 00 00 209 mov dptr,#s_XSEG
0119 E4 210 clr a
011A F0 211 00004$: movx @dptr,a
011B A3 212 inc dptr
011C D8 FC 213 djnz r0,00004$
011E D9 FA 214 djnz r1,00004$
0120 F6 215 00005$: mov @r0,a
0121 D8 FD 216 djnz r0,00005$
217 ; _mcs51_genRAMCLEAR() end
218 .area GSFINAL (CODE)
0123 02 00 2C 219 ljmp __sdcc_program_startup
220 ;--------------------------------------------------------
221 ; Home
222 ;--------------------------------------------------------
223 .area HOME (CODE)
224 .area CSEG (CODE)
225 ;--------------------------------------------------------
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