hubmd_next.h

这个linux源代码是很全面的~基本完整了~使用c编译的~由于时间问题我没有亲自测试~但就算用来做参考资料也是非常好的

/* $Id$
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
 */
#ifndef _ASM_IA64_SN_SN1_HUBMD_NEXT_H
#define _ASM_IA64_SN_SN1_HUBMD_NEXT_H

/* XXX moved over from SN/SN0/hubmd.h -- each should be checked for SN1 */
/* In fact, most of this stuff is wrong. Some is correct, such as
 * MD_PAGE_SIZE and MD_PAGE_NUM_SHFT.
 */

#define MD_PERF_COUNTERS        6
#define MD_PERF_SETS            6

#define MD_SIZE_EMPTY           0       
#define MD_SIZE_64MB            1       
#define MD_SIZE_128MB           2       
#define MD_SIZE_256MB           3
#define MD_SIZE_512MB           4      
#define MD_SIZE_1GB             5      

#define MD_SIZE_BYTES(size)     ((size) == 0 ? 0 : 0x2000000L << (size))
#define MD_SIZE_MBYTES(size)    ((size) == 0 ? 0 :   0x20       << (size))
#define MD_NUM_ENABLED(_x)	((_x & 0x1) + ((_x >> 1) & 0x1) + \
				((_x >> 2) & 0x1) + ((_x >> 3) & 0x1))


/* Hardware page size and shift */

#define MD_PAGE_SIZE            16384    /* Page size in bytes              */
#define MD_PAGE_NUM_SHFT        14       /* Address to page number shift    */

#define MMC_IO_PROT 		(UINT64_CAST 1 << 45)

/* Register offsets from LOCAL_HUB or REMOTE_HUB */
#define MD_PERF_SEL             0x210000 /* Select perf monitor events      */

/* MD_MIG_VALUE_THRESH bit definitions */

#define MD_MIG_VALUE_THRES_VALID_MASK (UINT64_CAST 0x1 << 63)
#define MD_MIG_VALUE_THRES_VALUE_MASK (UINT64_CAST 0xfffff)

/* MD_MIG_CANDIDATE bit definitions */

#define MD_MIG_CANDIDATE_VALID_MASK (UINT64_CAST 0x1 << 63)
#define MD_MIG_CANDIDATE_VALID_SHFT 63
#define MD_MIG_CANDIDATE_TYPE_MASK (UINT64_CAST 0x1 << 30)
#define MD_MIG_CANDIDATE_TYPE_SHFT 30
#define MD_MIG_CANDIDATE_OVERRUN_MASK (UINT64_CAST 0x1 << 29)
#define MD_MIG_CANDIDATE_OVERRUN_SHFT 29
#define MD_MIG_CANDIDATE_NODEID_MASK (UINT64_CAST 0x1ff << 20)
#define MD_MIG_CANDIDATE_NODEID_SHFT 20
#define MD_MIG_CANDIDATE_ADDR_MASK (UINT64_CAST 0x3ffff)


/* XXX protection and migration are completely revised on SN1.  On
   SN0, the reference count and protection fields were accessed in the
   same word, but on SN1 they reside at different addresses.  The
   users of these macros will need to be rewritten.  Also, the MD page
   size is 16K on SN1 but 4K on SN0.  */

/* Premium SIMM protection entry shifts and masks. */

#define MD_PPROT_SHFT           0                       /* Prot. field      */
#define MD_PPROT_MASK           0xf
#define MD_PPROT_REFCNT_SHFT    5                       /* Reference count  */
#define MD_PPROT_REFCNT_WIDTH   0x7ffff
#define MD_PPROT_REFCNT_MASK    (MD_PPROT_REFCNT_WIDTH << 5)

#define MD_PPROT_IO_SHFT        8                       /* I/O Prot field   */

/* Standard SIMM protection entry shifts and masks. */

#define MD_SPROT_SHFT           0                       /* Prot. field      */
#define MD_SPROT_MASK           0xf
#define MD_SPROT_IO_SHFT	8
#define MD_SPROT_REFCNT_SHFT    5                       /* Reference count  */
#define MD_SPROT_REFCNT_WIDTH   0x7ff
#define MD_SPROT_REFCNT_MASK    (MD_SPROT_REFCNT_WIDTH << 5)

/* Migration modes used in protection entries */

#define MD_PROT_MIGMD_IREL      (UINT64_CAST 0x3 << 3)
#define MD_PROT_MIGMD_IABS      (UINT64_CAST 0x2 << 3)
#define MD_PROT_MIGMD_PREL      (UINT64_CAST 0x1 << 3)
#define MD_PROT_MIGMD_OFF       (UINT64_CAST 0x0 << 3)

/*
 * Operations on Memory/Directory DIMM control register
 */

#define DIRTYPE_PREMIUM 1
#define DIRTYPE_STANDARD 0

/*
 * Operations on page migration count difference and absolute threshold
 * registers
 */

#define MD_MIG_VALUE_THRESH_GET(region) (                               \
        REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH) &  \
        MD_MIG_VALUE_THRES_VALUE_MASK)

#define MD_MIG_VALUE_THRESH_SET(region, value) (                        \
        REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH,                     \
                MD_MIG_VALUE_THRES_VALID_MASK | (value)))

#define MD_MIG_VALUE_THRESH_ENABLE(region) (                    \
        REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH,                     \
                REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH)             \
                             | MD_MIG_VALUE_THRES_VALID_MASK))

/*
 * Operations on page migration candidate register
 */

#define MD_MIG_CANDIDATE_GET(my_region_id) ( \
        REMOTE_HUB_L((my_region_id), MD_MIG_CANDIDATE_CLR))

#define MD_MIG_CANDIDATE_HWPFN(value) ((value) & MD_MIG_CANDIDATE_ADDR_MASK)

#define MD_MIG_CANDIDATE_NODEID(value) ( \
        ((value) & MD_MIG_CANDIDATE_NODEID_MASK) >> MD_MIG_CANDIDATE_NODEID_SHFT)

#define MD_MIG_CANDIDATE_TYPE(value) ( \
        ((value) & MD_MIG_CANDIDATE_TYPE_MASK) >> MD_MIG_CANDIDATE_TYPE_SHFT)

#define MD_MIG_CANDIDATE_VALID(value) ( \
        ((value) & MD_MIG_CANDIDATE_VALID_MASK) >> MD_MIG_CANDIDATE_VALID_SHFT)

/*
 * Macros to retrieve fields in the protection entry
 */

/* for Premium SIMM */
#define MD_PPROT_REFCNT_GET(value) ( \
        ((value) & MD_PPROT_REFCNT_MASK) >> MD_PPROT_REFCNT_SHFT)

/* for Standard SIMM */
#define MD_SPROT_REFCNT_GET(value) ( \
        ((value) & MD_SPROT_REFCNT_MASK) >> MD_SPROT_REFCNT_SHFT)

#ifndef __ASSEMBLY__
#ifdef LITTLE_ENDIAN

typedef union md_perf_sel {
        uint64_t      perf_sel_reg;
        struct  {
                uint64_t      perf_sel  :  3,
				perf_en   :  1,
				perf_rsvd : 60;
        } perf_sel_bits;
} md_perf_sel_t;

#else

typedef union md_perf_sel {
	uint64_t	perf_sel_reg;
	struct	{
		uint64_t	perf_rsvd : 60,
				perf_en	  :  1,
				perf_sel  :  3;
	} perf_sel_bits;
} md_perf_sel_t;

#endif
#endif /* __ASSEMBLY__ */


/* Like SN0, SN1 supports a mostly-flat address space with 8
   CPU-visible, evenly spaced, contiguous regions, or "software
   banks".  On SN1, software bank n begins at addresses n * 1GB, 
   0 <= n < 8.

   Physically (and very unlike SN0), each SN1 node board contains 8
   dimm sockets, arranged as 4 "DIMM banks" of 2 dimms each.  DIMM
   size and width (x4/x8) is assigned per dimm bank.  Each DIMM bank
   consists of 2 "physical banks", one on the front sides of the 2
   DIMMs and the other on the back sides.  Therefore a node has a
   total of 8 ( = 4 * 2) physical banks.  They are collectively
   referred to as "locational banks", since the locational bank number
   depends on the physical location of the DIMMs on the board.

	      Dimm bank 0, Phys bank 0a (locational bank 0a)
     Slot D0  ----------------------------------------------
	      Dimm bank 0, Phys bank 1a (locational bank 1a)

	      Dimm bank 1, Phys bank 0a (locational bank 2a)
     Slot D1  ----------------------------------------------
	      Dimm bank 1, Phys bank 1a (locational bank 3a)

	      Dimm bank 2, Phys bank 0a (locational bank 4a)
     Slot D2  ----------------------------------------------
	      Dimm bank 2, Phys bank 1a (locational bank 5a)

	      Dimm bank 3, Phys bank 0a (locational bank 6a)
     Slot D3  ----------------------------------------------
	      Dimm bank 3, Phys bank 1a (locational bank 7a)

	      Dimm bank 0, Phys bank 0b (locational bank 0b)
     Slot D4  ----------------------------------------------
	      Dimm bank 0, Phys bank 1b (locational bank 1b)

	      Dimm bank 1, Phys bank 0b (locational bank 2b)
     Slot D5  ----------------------------------------------
	      Dimm bank 1, Phys bank 1b (locational bank 3b)

	      Dimm bank 2, Phys bank 0b (locational bank 4b)
     Slot D6  ----------------------------------------------
	      Dimm bank 2, Phys bank 1b (locational bank 5b)

	      Dimm bank 3, Phys bank 0b (locational bank 6b)
     Slot D7  ----------------------------------------------
	      Dimm bank 3, Phys bank 1b (locational bank 7b)

   Since bank size is assigned per DIMM bank, each pair of locational
   banks must have the same size.  However, they may be
   enabled/disabled individually.

   The locational banks map to the software banks via the dimm0_sel
   field in MD_MEMORY_CONFIG.  When the field is 0 (the usual case),
   the mapping is direct:  eg. locational bank 1 (dimm bank 0,
   physical bank 1, which is the back side of the first DIMM pair)
   corresponds to software bank 1, at node offset 1GB.  More
   generally, locational bank = software bank XOR dimm0_sel.

   All the PROM's data structures (promlog variables, klconfig, etc.)
   track memory by the locational bank number.  The kernel usually
   tracks memory by the software bank number.
   memsupport.c:slot_psize_compute() performs the mapping.

   (Note:  the terms "locational bank" and "software bank" are not
   offical in any way, but I've tried to make the PROM use them
   consistently -- bjj.)
 */

#define MD_MEM_BANKS 		8
#define MD_MEM_DIMM_BANKS 	4
#define MD_BANK_SHFT            30                     /* log2(1 GB)     */
#define MD_BANK_MASK            (UINT64_CAST 0x7 << 30)
#define MD_BANK_SIZE            (UINT64_CAST 1 << MD_BANK_SHFT)   /*  1 GB */
#define MD_BANK_OFFSET(_b)      (UINT64_CAST (_b) << MD_BANK_SHFT)
#define MD_BANK_GET(addr)	(((addr) & MD_BANK_MASK) >> MD_BANK_SHFT)
#define MD_BANK_TO_DIMM_BANK(_b) (( (_b) >> 1) & 0x3)
#define MD_BANK_TO_PHYS_BANK(_b) (( (_b) >> 0) & 0x1)
#define MD_DIMM_BANK_GET(addr)   MD_BANK_TO_DIMM_BANK(MD_BANK_GET(addr))
#define MD_PHYS_BANK_GET(addr)   MD_BANK_TO_PHYS_BANK(MD_BANK_GET(addr))


/* Split an MD pointer (or message source & suppl. fields) into node, device */

#define MD_PTR_NODE_SHFT	3
#define MD_PTR_DEVICE_MASK	0x7
#define MD_PTR_SUBNODE0_MASK	0x1
#define MD_PTR_SUBNODE1_MASK	0x4


/**********************************************************************

 Backdoor protection and page counter structures

**********************************************************************/

/* Protection entries and page counters are interleaved at 4 separate
   addresses, 0x10 apart.  Software must read/write all four. */

#define BD_ITLV_COUNT		4
#define BD_ITLV_STRIDE		0x10

/* Protection entries */

/* (these macros work for standard (_rgn < 32) or premium DIMMs) */
#define MD_PROT_SHFT(_rgn, _io)	((((_rgn) & 0x20) >> 2 | \
				  ((_rgn) & 0x01) << 2 | \
				  ((_io)  &  0x1) << 1) * 8)
#define MD_PROT_MASK(_rgn, _io)	(0xff << MD_PROT_SHFT(_rgn, _io))
#define MD_PROT_GET(_val, _rgn, _io) \
	(((_val) & MD_PROT_MASK(_rgn, _io)) >> MD_PROT_SHFT(_rgn, _io))

/* Protection field values */

#define MD_PROT_RW              (UINT64_CAST 0xff)
#define MD_PROT_RO              (UINT64_CAST 0x0f)
#define MD_PROT_NO              (UINT64_CAST 0x00)




/**********************************************************************

 Directory format structures

***********************************************************************/

#ifndef __ASSEMBLY__

/* Standard Directory Entries */

#ifdef LITTLE_ENDIAN

struct	md_sdir_pointer_fmt { /* exclusive, busy shared/excl, wait, poisoned */
	bdrkreg_t	sdp_format                :	 2;
        bdrkreg_t       sdp_state                 :      3;
        bdrkreg_t       sdp_priority              :      3;
        bdrkreg_t       sdp_pointer1              :      8;
        bdrkreg_t       sdp_ecc                   :      6;
        bdrkreg_t       sdp_locprot               :      1;
        bdrkreg_t       sdp_reserved              :      1;
        bdrkreg_t       sdp_crit_word_off         :      3;
        bdrkreg_t       sdp_pointer2              :      5;
        bdrkreg_t       sdp_fill                  :     32;
};

#else

struct	md_sdir_pointer_fmt { /* exclusive, busy shared/excl, wait, poisoned */
	bdrkreg_t	sdp_fill		  :	32;
	bdrkreg_t	sdp_pointer2		  :	 5;
	bdrkreg_t	sdp_crit_word_off	  :	 3;
	bdrkreg_t	sdp_reserved		  :	 1;
	bdrkreg_t	sdp_locprot		  :	 1;
	bdrkreg_t	sdp_ecc			  :	 6;
	bdrkreg_t	sdp_pointer1		  :	 8;
	bdrkreg_t	sdp_priority		  :	 3;
	bdrkreg_t	sdp_state		  :	 3;
	bdrkreg_t	sdp_format		  :	 2;
};

#endif

#ifdef LITTLE_ENDIAN

struct	md_sdir_fine_fmt { /* shared (fine) */
	bdrkreg_t	sdf_format                :	 2;
        bdrkreg_t       sdf_tag1                  :      3;
        bdrkreg_t       sdf_tag2                  :      3;
        bdrkreg_t       sdf_vector1               :      8;
        bdrkreg_t       sdf_ecc                   :      6;
        bdrkreg_t       sdf_locprot               :      1;
        bdrkreg_t       sdf_tag2valid             :      1;
        bdrkreg_t       sdf_vector2               :      8;
        bdrkreg_t       sdf_fill                  :     32;
};

#else

struct	md_sdir_fine_fmt { /* shared (fine) */
	bdrkreg_t	sdf_fill		  :	32;
	bdrkreg_t	sdf_vector2		  :	 8;
	bdrkreg_t	sdf_tag2valid		  :	 1;
	bdrkreg_t	sdf_locprot		  :	 1;
	bdrkreg_t	sdf_ecc			  :	 6;
	bdrkreg_t	sdf_vector1		  :	 8;
	bdrkreg_t	sdf_tag2		  :	 3;
	bdrkreg_t	sdf_tag1		  :	 3;
	bdrkreg_t	sdf_format		  :	 2;
};

#endif

#ifdef LITTLE_ENDIAN

struct	md_sdir_coarse_fmt { /* shared (coarse) */
	bdrkreg_t	sdc_format                :	 2;
        bdrkreg_t       sdc_reserved_1            :      6;
        bdrkreg_t       sdc_vector_a              :      8;
        bdrkreg_t       sdc_ecc                   :      6;
        bdrkreg_t       sdc_locprot               :      1;
        bdrkreg_t       sdc_reserved              :      1;
        bdrkreg_t       sdc_vector_b              :      8;
        bdrkreg_t       sdc_fill                  :     32;
};

#else

struct	md_sdir_coarse_fmt { /* shared (coarse) */
	bdrkreg_t	sdc_fill		  :	32;
	bdrkreg_t	sdc_vector_b		  :	 8;
	bdrkreg_t	sdc_reserved		  :	 1;
	bdrkreg_t	sdc_locprot		  :	 1;
	bdrkreg_t	sdc_ecc			  :	 6;
	bdrkreg_t	sdc_vector_a		  :	 8;
	bdrkreg_t	sdc_reserved_1		  :	 6;
	bdrkreg_t	sdc_format		  :	 2;
};

#endif

typedef union md_sdir {
	/* The 32 bits of standard directory, in bits 31:0 */
	uint64_t	sd_val;
	struct	md_sdir_pointer_fmt	sdp_fmt;
	struct	md_sdir_fine_fmt	sdf_fmt;
	struct	md_sdir_coarse_fmt	sdc_fmt;
} md_sdir_t;


/* Premium Directory Entries */

#ifdef LITTLE_ENDIAN

struct	md_pdir_pointer_fmt { /* exclusive, busy shared/excl, wait, poisoned */