sb1250_scd.h

这个linux源代码是很全面的~基本完整了~使用c编译的~由于时间问题我没有亲自测试~但就算用来做参考资料也是非常好的

/*  *********************************************************************
    *  SB1250 Board Support Package
    *
    *  SCD Constants and Macros			File: sb1250_scd.h
    *
    *  This module contains constants and macros useful for
    *  manipulating the System Control and Debug module on the 1250.
    *
    *  SB1250 specification level:  User's manual 1/02/02
    *
    *  Author:  Mitch Lichtenberg ([e-mail])
    *
    *********************************************************************
    *
    *  Copyright 2000,2001
    *  Broadcom Corporation. All rights reserved.
    *
    *  This program is free software; you can redistribute it and/or
    *  modify it under the terms of the GNU General Public License as
    *  published by the Free Software Foundation; either version 2 of
    *  the License, or (at your option) any later version.
    *
    *  This program is distributed in the hope that it will be useful,
    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    *  GNU General Public License for more details.
    *
    *  You should have received a copy of the GNU General Public License
    *  along with this program; if not, write to the Free Software
    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
    *  MA 02111-1307 USA
    ********************************************************************* */

#ifndef _SB1250_SCD_H
#define _SB1250_SCD_H

#include "sb1250_defs.h"

/*  *********************************************************************
    *  System control/debug registers
    ********************************************************************* */

/*
 * System Revision Register (Table 4-1)
 */

#define M_SYS_RESERVED		    _SB_MAKEMASK(8,0)

#define S_SYS_REVISION              _SB_MAKE64(8)
#define M_SYS_REVISION              _SB_MAKEMASK(8,S_SYS_REVISION)
#define V_SYS_REVISION(x)           _SB_MAKEVALUE(x,S_SYS_REVISION)
#define G_SYS_REVISION(x)           _SB_GETVALUE(x,S_SYS_REVISION,M_SYS_REVISION)

#define K_SYS_REVISION_PASS1	    1
#define K_SYS_REVISION_PASS2	    3
#define K_SYS_REVISION_PASS2_2	    16
#define K_SYS_REVISION_PASS3	    32

#define S_SYS_PART                  _SB_MAKE64(16)
#define M_SYS_PART                  _SB_MAKEMASK(16,S_SYS_PART)
#define V_SYS_PART(x)               _SB_MAKEVALUE(x,S_SYS_PART)
#define G_SYS_PART(x)               _SB_GETVALUE(x,S_SYS_PART,M_SYS_PART)

#define K_SYS_PART_SB1250           0x1250
#define K_SYS_PART_SB1125           0x1125

#define S_SYS_WID                   _SB_MAKE64(32)
#define M_SYS_WID                   _SB_MAKEMASK(32,S_SYS_WID)
#define V_SYS_WID(x)                _SB_MAKEVALUE(x,S_SYS_WID)
#define G_SYS_WID(x)                _SB_GETVALUE(x,S_SYS_WID,M_SYS_WID)

/*
 * System Config Register (Table 4-2)
 * Register: SCD_SYSTEM_CFG
 */

#define M_SYS_LDT_PLL_BYP           _SB_MAKEMASK1(3)
#define M_SYS_PCI_SYNC_TEST_MODE    _SB_MAKEMASK1(4)
#define M_SYS_IOB0_DIV              _SB_MAKEMASK1(5)
#define M_SYS_IOB1_DIV              _SB_MAKEMASK1(6)

#define S_SYS_PLL_DIV               _SB_MAKE64(7)
#define M_SYS_PLL_DIV               _SB_MAKEMASK(5,S_SYS_PLL_DIV)
#define V_SYS_PLL_DIV(x)            _SB_MAKEVALUE(x,S_SYS_PLL_DIV)
#define G_SYS_PLL_DIV(x)            _SB_GETVALUE(x,S_SYS_PLL_DIV,M_SYS_PLL_DIV)

#define M_SYS_SER0_ENABLE           _SB_MAKEMASK1(12)
#define M_SYS_SER0_RSTB_EN          _SB_MAKEMASK1(13)
#define M_SYS_SER1_ENABLE           _SB_MAKEMASK1(14)
#define M_SYS_SER1_RSTB_EN          _SB_MAKEMASK1(15)
#define M_SYS_PCMCIA_ENABLE         _SB_MAKEMASK1(16)

#define S_SYS_BOOT_MODE             _SB_MAKE64(17)
#define M_SYS_BOOT_MODE             _SB_MAKEMASK(2,S_SYS_BOOT_MODE)
#define V_SYS_BOOT_MODE(x)          _SB_MAKEVALUE(x,S_SYS_BOOT_MODE)
#define G_SYS_BOOT_MODE(x)          _SB_GETVALUE(x,S_SYS_BOOT_MODE,M_SYS_BOOT_MODE)
#define K_SYS_BOOT_MODE_ROM32       0
#define K_SYS_BOOT_MODE_ROM8        1
#define K_SYS_BOOT_MODE_SMBUS_SMALL 2
#define K_SYS_BOOT_MODE_SMBUS_BIG   3

#define M_SYS_PCI_HOST              _SB_MAKEMASK1(19)
#define M_SYS_PCI_ARBITER           _SB_MAKEMASK1(20)
#define M_SYS_SOUTH_ON_LDT          _SB_MAKEMASK1(21)
#define M_SYS_BIG_ENDIAN            _SB_MAKEMASK1(22)
#define M_SYS_GENCLK_EN             _SB_MAKEMASK1(23)
#define M_SYS_LDT_TEST_EN           _SB_MAKEMASK1(24)
#define M_SYS_GEN_PARITY_EN         _SB_MAKEMASK1(25)

#define S_SYS_CONFIG                26
#define M_SYS_CONFIG                _SB_MAKEMASK(6,S_SYS_CONFIG)
#define V_SYS_CONFIG(x)             _SB_MAKEVALUE(x,S_SYS_CONFIG)
#define G_SYS_CONFIG(x)             _SB_GETVALUE(x,S_SYS_CONFIG,M_SYS_CONFIG)

/* The following bits are writeable by JTAG only. */

#define M_SYS_CLKSTOP               _SB_MAKEMASK1(32)
#define M_SYS_CLKSTEP               _SB_MAKEMASK1(33)

#define S_SYS_CLKCOUNT              34
#define M_SYS_CLKCOUNT              _SB_MAKEMASK(8,S_SYS_CLKCOUNT)
#define V_SYS_CLKCOUNT(x)           _SB_MAKEVALUE(x,S_SYS_CLKCOUNT)
#define G_SYS_CLKCOUNT(x)           _SB_GETVALUE(x,S_SYS_CLKCOUNT,M_SYS_CLKCOUNT)

#define M_SYS_PLL_BYPASS            _SB_MAKEMASK1(42)

#define S_SYS_PLL_IREF		    43
#define M_SYS_PLL_IREF		    _SB_MAKEMASK(2,S_SYS_PLL_IREF)

#define S_SYS_PLL_VCO		    45
#define M_SYS_PLL_VCO		    _SB_MAKEMASK(2,S_SYS_PLL_VCO)

#define S_SYS_PLL_VREG		    47
#define M_SYS_PLL_VREG		    _SB_MAKEMASK(2,S_SYS_PLL_VREG)

#define M_SYS_MEM_RESET             _SB_MAKEMASK1(49)
#define M_SYS_L2C_RESET             _SB_MAKEMASK1(50)
#define M_SYS_IO_RESET_0            _SB_MAKEMASK1(51)
#define M_SYS_IO_RESET_1            _SB_MAKEMASK1(52)
#define M_SYS_SCD_RESET             _SB_MAKEMASK1(53)

/* End of bits writable by JTAG only. */

#define M_SYS_CPU_RESET_0           _SB_MAKEMASK1(54)
#define M_SYS_CPU_RESET_1           _SB_MAKEMASK1(55)

#define M_SYS_UNICPU0               _SB_MAKEMASK1(56)
#define M_SYS_UNICPU1               _SB_MAKEMASK1(57)

#define M_SYS_SB_SOFTRES            _SB_MAKEMASK1(58)
#define M_SYS_EXT_RESET             _SB_MAKEMASK1(59)
#define M_SYS_SYSTEM_RESET          _SB_MAKEMASK1(60)

#define M_SYS_MISR_MODE             _SB_MAKEMASK1(61)
#define M_SYS_MISR_RESET            _SB_MAKEMASK1(62)

#define M_SYS_SW_FLAG		    _SB_MAKEMASK1(63)	/* PASS2 */


/*
 * Mailbox Registers (Table 4-3)
 * Registers: SCD_MBOX_CPU_x
 */

#define S_MBOX_INT_3                0
#define M_MBOX_INT_3                _SB_MAKEMASK(16,S_MBOX_INT_3)
#define S_MBOX_INT_2                16
#define M_MBOX_INT_2                _SB_MAKEMASK(16,S_MBOX_INT_2)
#define S_MBOX_INT_1                32
#define M_MBOX_INT_1                _SB_MAKEMASK(16,S_MBOX_INT_1)
#define S_MBOX_INT_0                48
#define M_MBOX_INT_0                _SB_MAKEMASK(16,S_MBOX_INT_0)

/*
 * Watchdog Registers (Table 4-8) (Table 4-9) (Table 4-10)
 * Registers: SCD_WDOG_INIT_CNT_x
 */

#define V_SCD_WDOG_FREQ             1000000

#define S_SCD_WDOG_INIT             0
#define M_SCD_WDOG_INIT             _SB_MAKEMASK(13,S_SCD_WDOG_INIT)

#define S_SCD_WDOG_CNT              0
#define M_SCD_WDOG_CNT              _SB_MAKEMASK(13,S_SCD_WDOG_CNT)

#define M_SCD_WDOG_ENABLE           _SB_MAKEMASK1(0)

/*
 * Timer Registers (Table 4-11) (Table 4-12) (Table 4-13)
 */

#define V_SCD_TIMER_FREQ            1000000

#define S_SCD_TIMER_INIT            0
#define M_SCD_TIMER_INIT            _SB_MAKEMASK(20,S_SCD_TIMER_INIT)
#define V_SCD_TIMER_INIT(x)         _SB_MAKEVALUE(x,S_SCD_TIMER_INIT)
#define G_SCD_TIMER_INIT(x)         _SB_GETVALUE(x,S_SCD_TIMER_INIT,M_SCD_TIMER_INIT)

#define S_SCD_TIMER_CNT             0
#define M_SCD_TIMER_CNT             _SB_MAKEMASK(20,S_SCD_TIMER_CNT)
#define V_SCD_TIMER_CNT(x)         _SB_MAKEVALUE(x,S_SCD_TIMER_CNT)
#define G_SCD_TIMER_CNT(x)         _SB_GETVALUE(x,S_SCD_TIMER_CNT,M_SCD_TIMER_CNT)

#define M_SCD_TIMER_ENABLE          _SB_MAKEMASK1(0)
#define M_SCD_TIMER_MODE            _SB_MAKEMASK1(1)
#define M_SCD_TIMER_MODE_CONTINUOUS M_SCD_TIMER_MODE

/*
 * System Performance Counters
 */

#define S_SPC_CFG_SRC0            0
#define M_SPC_CFG_SRC0            _SB_MAKEMASK(8,S_SPC_CFG_SRC0)
#define V_SPC_CFG_SRC0(x)         _SB_MAKEVALUE(x,S_SPC_CFG_SRC0)
#define G_SPC_CFG_SRC0(x)         _SB_GETVALUE(x,S_SPC_CFG_SRC0,M_SPC_CFG_SRC0)

#define S_SPC_CFG_SRC1            8
#define M_SPC_CFG_SRC1            _SB_MAKEMASK(8,S_SPC_CFG_SRC1)
#define V_SPC_CFG_SRC1(x)         _SB_MAKEVALUE(x,S_SPC_CFG_SRC1)
#define G_SPC_CFG_SRC1(x)         _SB_GETVALUE(x,S_SPC_CFG_SRC1,M_SPC_CFG_SRC1)

#define S_SPC_CFG_SRC2            16
#define M_SPC_CFG_SRC2            _SB_MAKEMASK(8,S_SPC_CFG_SRC2)
#define V_SPC_CFG_SRC2(x)         _SB_MAKEVALUE(x,S_SPC_CFG_SRC2)
#define G_SPC_CFG_SRC2(x)         _SB_GETVALUE(x,S_SPC_CFG_SRC2,M_SPC_CFG_SRC2)

#define S_SPC_CFG_SRC3            24
#define M_SPC_CFG_SRC3            _SB_MAKEMASK(8,S_SPC_CFG_SRC3)
#define V_SPC_CFG_SRC3(x)         _SB_MAKEVALUE(x,S_SPC_CFG_SRC3)
#define G_SPC_CFG_SRC3(x)         _SB_GETVALUE(x,S_SPC_CFG_SRC3,M_SPC_CFG_SRC3)

#define M_SPC_CFG_CLEAR		_SB_MAKEMASK1(32)