8253xini.c

这个linux源代码是很全面的~基本完整了~使用c编译的~由于时间问题我没有亲自测试~但就算用来做参考资料也是非常好的

/* -*- linux-c -*- */
/* 
 * Copyright (C) 2001 By Joachim Martillo, Telford Tools, Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 *
 **/

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/stddef.h>
#include <linux/string.h>
#include <linux/sockios.h>
#include <asm/io.h>
#include <asm/byteorder.h>
#include <asm/pgtable.h>
#include <linux/skbuff.h>
#include <linux/if_arp.h>
#include <linux/fs.h>
#include <linux/sched.h>
#include <asm/uaccess.h>
#include <linux/version.h>
#include <linux/etherdevice.h>
#include <linux/init.h>
#include "Reg9050.h"
#include "8253xctl.h"
#include "ring.h"
#include "8253x.h"
#include "crc32dcl.h"
#include "8253xmcs.h"
#include "sp502.h"

/* card names */

char *aura_functionality[] =
{
	"NR",
	"AO",
	"NA",
	"UN"
};

char *board_type[] =
{
	"unknown",
	"1020P",
	"1520P",
	"2020P",
	"2520P",
	"4020P",
	"4520P",
	"8020P",
	"8520P",
	"SUNSE",
	"WANMS",
	"1020C",
	"1520C",
	"2020C",
	"2520C",
	"4020C",
	"4520C",
	"8020C",
	"8520C",
};

unsigned int sab8253x_rebootflag = 0;

AURAXX20PARAMS AuraXX20DriverParams; /* loaded at startup */
				/* from variables below */
SAB_BOARD *AuraBoardRoot = NULL; /* The order of this list is not important */
SAB_CHIP  *AuraChipRoot = NULL;	/* chips grouped by board chip0 before chip1 */
SAB_PORT  *AuraPortRoot = NULL;	/* ports grouped by board and by chip, chip0, chip1, etc */
AURA_CIM  *AuraCimRoot = NULL;	/* only used for deallocating the cim structures, etc */
/* CIM stands for Communications Interface Module -- the G.Link logic provided by the Altera parts. */

/* Arrays of lists of boards of each type on a given interrupt */
SAB_BOARD *AuraBoardESCC2IrqRoot[NUMINTS]; 
SAB_BOARD *AuraBoardESCC8IrqRoot[NUMINTS];
SAB_BOARD *AuraBoardMCSIrqRoot[NUMINTS];

unsigned int NumSab8253xPorts = 0;

unsigned BD1020Pcounter = 0;	/* keep count of each board */
unsigned BD1520Pcounter = 0;	/* may change to just keeping count */
unsigned BD2020Pcounter = 0;	/* of the total number of boards */
unsigned BD2520Pcounter = 0;
unsigned BD4020Pcounter = 0;
unsigned BD4520Pcounter = 0;
unsigned BD8020Pcounter = 0;
unsigned BD8520Pcounter = 0;

unsigned BD1020CPcounter = 0;	/* keep count of each board */
unsigned BD1520CPcounter = 0;	/* may change to just keeping count */
unsigned BD2020CPcounter = 0;	/* of the total number of boards */
unsigned BD2520CPcounter = 0;
unsigned BD4020CPcounter = 0;
unsigned BD4520CPcounter = 0;
unsigned BD8020CPcounter = 0;
unsigned BD8520CPcounter = 0;

unsigned BDMCScounter = 0;


static int auraXX20n_debug = 0;	/* turns on lots of */
				/* debugging messages*/
static char* auraXX20n_name = 0;/* set net dev name on command line */
static char *sab8253xc_name = "sab8253xc";
static int sab8253xc_major = 0;
int sab8253xn_listsize = 32; /* recommend descriptor list size */
int sab8253xn_rbufsize = RXSIZE; /* recommend rbuf list size */
int sab8253xt_listsize = 256; /* recommend descriptor list size */
int sab8253xt_rbufsize = 32; /* recommend rbuf list size for tty */
int sab8253xs_listsize = 64; /* recommend descriptor list size */
int sab8253xs_rbufsize = RXSIZE; /* recommend rbuf list size */
int sab8253xc_listsize = 64; /* recommend descriptor list size */
int sab8253xc_rbufsize = RXSIZE; /* recommend rbuf list size for tty */
int xx20_minorstart = 128;
int sab8253x_vendor_id = PCI_VENDOR_ID_AURORATECH;
int sab8253x_cpci_device_id = PCI_DEVICE_ID_AURORATECH_CPCI;
int sab8253x_wmcs_device_id = PCI_DEVICE_ID_AURORATECH_WANMS;
int sab8253x_mpac_device_id = PCI_DEVICE_ID_AURORATECH_MULTI;
int sab8253x_default_sp502_mode = SP502_RS232_MODE;

MODULE_LICENSE("GPL");

MODULE_PARM(sab8253x_vendor_id, "i");
MODULE_PARM(sab8253x_cpci_device_id, "i");
MODULE_PARM(sab8253x_wmcs_device_id, "i");
MODULE_PARM(sab8253x_mpac_device_id, "i");
MODULE_PARM(sab8253x_default_sp502_mode, "i");

MODULE_PARM(xx20_minorstart, "i");
MODULE_PARM(sab8253xc_major, "i");
MODULE_PARM(auraXX20n_debug, "i");
MODULE_PARM(auraXX20n_name, "s"); /* this and the following for sync */
MODULE_PARM(sab8253xn_listsize, "i"); /* network driver */
MODULE_PARM(sab8253xn_rbufsize, "i"); /* network driver */
MODULE_PARM(sab8253xt_listsize, "i"); /* tty driver */
MODULE_PARM(sab8253xt_rbufsize, "i"); /* tty driver */
MODULE_PARM(sab8253xc_listsize, "i"); /* network driver */
MODULE_PARM(sab8253xc_rbufsize, "i"); /* network driver */
MODULE_PARM(sab8253xs_listsize, "i"); /* tty driver */
MODULE_PARM(sab8253xs_rbufsize, "i"); /* tty driver */
MODULE_PARM(sab8253xc_name, "s"); 

struct pci_dev   *XX20lastpdev = NULL; /* just used for finding all PCI devices */
static SAB_BOARD *find_ati_multiport_card(void); /* actually implemented */
static SAB_BOARD *find_ati_cpci_card(void); /* to be done */
static SAB_BOARD *find_ati_wanms_card(void); /* to be done */

#if (!defined(MODULE)) && (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 0))
				/* unpleasantness for 2.2 kernels
				 * and probe illogic */

				/* The LRP project is still working on
				   2.2.* kernels but I suspect
				   that initially we will see more
				   purchases for complete Linux
				   machines using 2.4.*, LRP
				   machines tend to be underpowered
				   and have a paucity of PCI slots
				*/

unsigned int do_probe = 1;
#endif

				/* One could argue that these could be in  */
				/* the 8253xnet.c file but they are fairly */
				/* intimately involved with initialization.*/
struct net_device *Sab8253xRoot = NULL;

struct net_device auraXX20n_prototype = /* used for the network device */
{
	"8253x0",			
	0, 0, 0, 0,
	0x000,
	-1, /* bad irq */
	0, 0, 0,
	NULL,
	sab8253xn_init /* network driver initialization */
};

struct file_operations sab8253xc_fops =
{
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 4, 0))
	NULL,
#endif
	NULL,			/* llseek */
	sab8253xc_read,		/* read */
	sab8253xc_write,	/* write */
	NULL,			/* readdir */
	sab8253xc_poll,		/* poll */
	sab8253xc_ioctl,	/* ioctl */
	NULL,			/* mmap */
	sab8253xc_open,		/* open */
	NULL,			/* flush */
	sab8253xc_release,	/* release */
	NULL,			/* fsync */
	sab8253xc_fasync,	/* fasync */
	NULL,			/* check_media_change */
	NULL,			/* revalidate */
	NULL			/* lock */
};


/* A few function defined in this file */
/* These functions are basically functionality */
/* independent -- they are used with asynchronous ttys */
/* synchronous ttys, the network device and the */
/* raw character device */

				/* used for reading and writing ports
				   readw and writew require some reprogramming
				   of the PLX9050
				*/
static unsigned char aura_readb(struct sab_port *port, unsigned char *reg);
static unsigned char wmsaura_readb(struct sab_port *port, unsigned char *reg);
static unsigned short aura_readw(struct sab_port *port, unsigned short *reg);
static unsigned short wmsaura_readw(struct sab_port *port, unsigned short *reg);
static void aura_writeb(struct sab_port *port, unsigned char *reg,unsigned char val);
static void wmsaura_writeb(struct sab_port *port, unsigned char *reg,unsigned char val);
static void aura_writew(struct sab_port *port, unsigned short *reg,unsigned short val);
static void wmsaura_writew(struct sab_port *port, unsigned short *reg,unsigned short val);

static void aura_readfifo(struct sab_port *port, unsigned char *buf, unsigned int nbytes);
static void aura_writefifo(struct sab_port *port);

static void wmsaura_readfifo(struct sab_port *port, unsigned char *buf, unsigned int nbytes);
static void wmsaura_writefifo(struct sab_port *port);

/* function definitions */

/* [124]X20 type cards */
static void DisableESCC2Interrupts(SAB_CHIP *chipptr) /* in processing ports may have to disable ints */
{
	struct sab82532_async_wr_regs *regs;
	
	regs = chipptr->c_regs;
	writeb(0xff,&regs->pim);	/* All interrupts off */
				/* Note that regs/->c_regs
				   is set to base reg
				   address, thus taking
				   address or regs->pim
				   gets the address of
				   the PIM register/int mask */
}

static SAB_CHIP* CreateESCC2(SAB_BOARD *bptr, unsigned int offset)
{
	SAB_CHIP *cptr;
	struct sab82532_async_wr_regs *regs;
	
	printk(KERN_ALERT 
	       "auraXX20n: creating ESCC2 structure on board %p at offset %x.\n",
	       bptr, offset);
	
	cptr = (SAB_CHIP*) kmalloc(sizeof(SAB_CHIP), GFP_KERNEL);
	if(cptr == NULL)
	{
		printk(KERN_ALERT
		       "auraXX20n: Failed to create ESCC2 structure on board %p at offset %x.\n",
		       bptr, offset);
		return NULL;
	}
	memset(cptr, 0, sizeof(SAB_CHIP));
	cptr->chip_type = ESCC2;
	cptr->c_board = bptr;
	cptr->c_cim = NULL;
	cptr->c_chipno = (offset ? 1 : 0); /* first or second chip on board */
	cptr->c_revision = 
		(readb(((char *)bptr->virtbaseaddress2) + offset + SAB85232_REG_VSTR) &
		 SAB82532_VSTR_VN_MASK);
	cptr->c_nports = 2;
	cptr->c_portbase = NULL;
	cptr->next = AuraChipRoot;	/* chips are added to chiplist in reverse order */
	AuraChipRoot = cptr;
	cptr->next_by_board = bptr->board_chipbase; /* likewise for the local board chiplist */
	bptr->board_chipbase = cptr;
	printk(KERN_ALERT "auraXX20n: chip %d on board %p is revision %d.\n",
	       cptr->c_chipno, bptr, cptr->c_revision);
	
	/* lets set up the generic parallel
	 * port register which is used to
	 * control signaling and other stuff*/
	/*
	 * SAB82532 (Aurora) 1 8-bit parallel port
	 * To summarize the use of the parallel port:
	 *                    RS-232
	 *  A       B        I/O     descr
	 * P0      P4      output  TxClk ctrl
	 * P1      P5      output  DTR
	 * P2      P6      input   DSR
	 * P3      P7      output  485 control
	 *
	 */
	/*
	 * Configuring the parallel port 
	 */
	
	regs = (struct sab82532_async_wr_regs *)(((char *)bptr->virtbaseaddress2) + offset);
	
	DEBUGPRINT((KERN_ALERT "Writing 0x44 to 0x%p + 0x%x for chip %d\n",
		    regs, SAB82532_REG_PCR, cptr->c_chipno));
	
	writeb(0x44,&regs->pcr);  /* 2 input bits */
	writeb(0xff,&regs->pim);/* All interrupts off */
	writeb(0x33,&regs->pvr); /* Txclk and DTR low  */
	
	cptr->c_regs = (void*) regs;
	cptr->int_disable = DisableESCC2Interrupts;
	return cptr;
}

static void CreateESCC2Port(SAB_CHIP *cptr, unsigned int portno, unsigned int function)
{
	SAB_BOARD *bptr;
	SAB_PORT  *pptr;
	extern void sab8253x_setup_ttyport(struct sab_port *p_port) ;
	
	++NumSab8253xPorts;
	bptr = cptr->c_board;
	pptr = (SAB_PORT*) kmalloc(sizeof(SAB_PORT), GFP_KERNEL);
	if(pptr == NULL)
	{
		printk(KERN_ALERT
		       "auraXX20n: Failed to create ESCC2 port structure on chip %p on board %p.\n",
		       cptr, bptr);
		return;
	}
	memset(pptr, 0, sizeof(SAB_PORT));
	DEBUGPRINT
		((KERN_ALERT "Setting up port %d, chipno %d for %s type board number %d.\n", 
		  portno, cptr->c_chipno, board_type[bptr->b_type],bptr->board_number));
	pptr->portno = portno;
	pptr->chip=cptr;
	pptr->board=bptr;
	pptr->open_type=OPEN_NOT;
	pptr->is_console=0;
	pptr->regs=
		(union sab82532_regs *)
		(((unsigned int)cptr->c_regs) +
		 (portno * SAB82532_REG_SIZE));
	pptr->type = cptr->c_revision;
	pptr->function = function;
	
	/* Simpify reading */
#define PVR  pptr->regs->async_write.pvr
#define PCR  pptr->regs->async_write.pcr
#define PIM  pptr->regs->async_write.pim
#define ISR0 pptr->regs->async_read.isr0
#define IMR0 pptr->regs->async_write.imr0
#define IMR1 pptr->regs->async_write.imr1
#define PIS  pptr->regs->async_read.pis
#define VSTR pptr->regs->async_read.vstr
#define STAR pptr->regs->async_read.star
#define MODE pptr->regs->async_read.mode
	
	pptr->irq = bptr->b_irq;
	if(portno == 0) 
	{ /* Port A .... */
		pptr->dsr.reg=(unsigned char *)&(PVR);
		pptr->dsr.mask=0x04;
		pptr->dsr.irq=PIS_IDX;
		pptr->dsr.irqmask=0x04;
		
		pptr->dtr.reg=(unsigned char *)&(PVR);
		pptr->dtr.mask=0x02;
		
		pptr->txclkdir.reg=(unsigned char *)&(PVR);
		pptr->txclkdir.mask=0x01;
	} 
	else 
	{ /* Port B */
		pptr->dsr.reg=(unsigned char *)&(PVR);
		pptr->dsr.mask=0x40;
		pptr->dsr.irq=PIS_IDX;
		pptr->dsr.irqmask=0x40;
		
		pptr->dtr.reg=(unsigned char *)&(PVR);
		pptr->dtr.mask=0x20;
		
		pptr->txclkdir.reg=(unsigned char *)&(PVR);
		pptr->txclkdir.mask=0x10;
	}
	pptr->dsr.inverted=1;
	pptr->dsr.cnst = 0;
	pptr->dtr.inverted=1;
	pptr->dtr.cnst = 0;
	pptr->txclkdir.inverted=1;
	
	pptr ->dcd.reg =(unsigned char *) &(VSTR);
	
	DEBUGPRINT((KERN_ALERT "cd register set to 0x%p\n", pptr ->dcd.reg));
	
	pptr->dcd.mask = SAB82532_VSTR_CD;
	pptr->dcd.inverted = 1;
	pptr->dcd.irq=ISR0_IDX;
	pptr->dcd.irqmask=SAB82532_ISR0_CDSC;
	pptr->dcd.cnst = 0;
	
	pptr->cts.reg = (unsigned char *)&(STAR);
	pptr->cts.mask = SAB82532_STAR_CTS;
	pptr->cts.inverted = 0;
	pptr->cts.irq=ISR1_IDX;
	pptr->cts.irqmask=SAB82532_ISR1_CSC;
	pptr->cts.cnst = 0;
	
	pptr->rts.reg = (unsigned char *)&(MODE);
	pptr->rts.mask = SAB82532_MODE_FRTS;
	pptr->rts.inverted = 1;
	pptr->rts.cnst = SAB82532_MODE_RTS;
	
	
	/* Set the read and write function */
	pptr->readbyte=aura_readb;
	pptr->readword=aura_readw;
	pptr->writebyte=aura_writeb;
	pptr->writeword=aura_writew;
	pptr->readfifo=aura_readfifo;
	pptr->writefifo=aura_writefifo;
	
	sab8253x_setup_ttyport(pptr);	/* asynchronous */
	/* ttys are default, basic */
	/* initialization, everything */
	/* else works as a modification */
	/* thereof */
	
	pptr->next = AuraPortRoot;
	AuraPortRoot = pptr;
	pptr->next_by_chip = cptr->c_portbase;
	cptr->c_portbase = pptr;
	pptr->next_by_board = bptr->board_portbase;