8253x.h

这个linux源代码是很全面的~基本完整了~使用c编译的~由于时间问题我没有亲自测试~但就算用来做参考资料也是非常好的

	struct sab_port * next_by_chip;
	struct sab_port * next_by_board;
	struct sab_port * next_by_cim;
	
	struct net_device *dev;
	struct net_device *next_dev;
	
	struct fasync_struct * async_queue;
	struct sk_buff_head *sab8253xbuflist; /* need to keep */
				/* a list of all */
				/* skbuffs so that */
				/* we can guarantee */
				/* freeing all when */
				/* the PPC is stopped */
				/* on close*/
	struct sk_buff_head *sab8253xc_rcvbuflist; /* used for passing */
				/* buffers from interrupt */
				/* receive process*/
	
	
	DCONTROL2 dcontrol2;
	DCONTROL2 active2;
	DCONTROL2 sabnext2;

	int			DoingInterrupt;
	int			irq;
	int			flags;	       /* suggested by serial.h
						* but this driver is
						* more general */
	int			syncflags;
	int			type;	       /* SAB82532/8 version */
	unsigned int		function;
	int			read_status_mask;
	int			ignore_status_mask;
	int			timeout;
	int			xmit_fifo_size;
	int			recv_fifo_size;
	int			custom_divisor;
	unsigned long		baud;
	unsigned int		ebrg;
	unsigned int		cec_timeout;
	unsigned int		tec_timeout;

	int			x_char;
	int			close_delay;
	unsigned short		closing_wait;
	unsigned short		closing_wait2;
	int			all_sent;
	int			is_console;
#define OPEN_NOT 0
#define OPEN_ASYNC 1
#define OPEN_SYNC 2
#define OPEN_BSC 3
#define OPEN_RAW 4
#define OPEN_SYNC_NET 5
#define OPEN_SYNC_CHAR 6
	unsigned int		open_type; /* Sync? Async?, int better for hw bps */
	unsigned char	        interrupt_mask0;
	unsigned char		interrupt_mask1;
				/* Modem signals */
	mctlsig_t		dtr;
	mctlsig_t		dsr;
	mctlsig_t		dcd;
	mctlsig_t		cts;
	mctlsig_t		rts;
	mctlsig_t		txclkdir; /* Direction of TxClk */
	unsigned long           custspeed; /* Custom speed */
	unsigned long		event;
	unsigned long		last_active;
	int			line;
	int			count;
	int			blocked_open;
	long			session;
	long			pgrp;
	struct tq_struct	tqueue;
	struct tq_struct	tqueue_hangup;
	struct async_icount	icount;
	struct termios		normal_termios;
	struct termios		callout_termios;
	wait_queue_head_t	open_wait;
	wait_queue_head_t	close_wait;
	wait_queue_head_t	delta_msr_wait;
	wait_queue_head_t	read_wait;
	wait_queue_head_t	write_wait;
  
  /*
   * Pointer to FIFO access routines.  These are individualized
   *  by hardware because different hardware may have different
   *  ways to get to the FIFOs.
   */
  
	void			(*readfifo)(struct sab_port *port, 
					    unsigned char *buf,
					    u32 nbytes);
	void			(*writefifo)(struct sab_port *port);
  
  /*
   * Pointer to register access routines.  These are individualized
   *  by hardware because different hardware may have different
   *  ways to get to the register.
   */
	unsigned char		(*readbyte)(struct sab_port *port, 
					    unsigned char *reg);
	void	        	(*writebyte)(struct sab_port *port, 
					     unsigned char *reg,
					     unsigned char val);
	u16			(*readword)(struct sab_port *port, 
					    u16 *reg);
	void	        	(*writeword)(struct sab_port *port, 
					     u16 *reg,
					     u16 val);
  
  /*
   * Pointer to protocol functions
   *
   */
  
	unsigned int portno;
	void (*receive_chars)(struct sab_port *port, 
			      union sab8253x_irq_status *stat);
	void (*transmit_chars)(struct sab_port *port,
			       union sab8253x_irq_status *stat);
	void (*check_status)(struct sab_port *port,
			     union sab8253x_irq_status *stat);
	unsigned int receive_test;
	unsigned int transmit_test;
	unsigned int check_status_test;
	struct channelcontrol ccontrol;
	
	unsigned int tx_full;
	unsigned int rx_empty;
	struct counters Counters;
	struct net_device_stats stats;
	
				/* collect statistics for netstat */
				/* etc.  those programs don't know */
				/* about priorities*/

	int			msgbufindex;
	char			msgbuf[RXSIZE];
	unsigned int		buffergreedy;
	unsigned int		sigmode;
} sab_port_t, SAB_PORT;

/*
 * per-parallel port structure
 */

/* SAB82538 4 8-bits parallel ports
 * To summarize the use of the parallel port:
 *                    RS-232
 * Parallel port A -- TxClkdir control	(output) ports 0 - 7
 * Parallel port B -- DTR		(output) ports 0 - 7
 * Parallel port C -- DSR		(input)  ports 0 - 7
 * Parallel port D -- driver power down	(output) drivers 0 - 3
 *
 * SAB82532 (Aurora) 1 8-bit parallel port
 * To summarize the use of the parallel port:
 *                    RS-232
 *  A       B        I/O     descr
 * P0      P4      output  TxClk ctrl
 * P1      P5      output  DTR
 * P2      P6      input   DSR
 * P3      P7      output  485 control
 *
 * Note that this new version of the driver
 * does not support the SPARC motherboard ESCC2
 *
 * SAB82532 (Sun) 1 8-bit parallel port
 * To summarize the use of the parallel port:
 *                    RS-232
 *  A       B        I/O     descr
 * P0      P3      input    DSR
 * P1      P2      output    DTR
 * P5      P6      input     ?
 * P4      P7      output    ?
 *
 */
				/* not sure how usefule */
typedef struct sabparport 
{
  /* cached values: */
	unsigned char	 pp_pcr;
	unsigned char	 pp_pim;
	unsigned char	 pp_pvr;
	
	/* register offsets: */
	unsigned int	 pp_pcrreg;
	unsigned int	 pp_pimreg;
	unsigned int	 pp_pisreg;
	unsigned int	 pp_pvrreg;
} sabparport_t, SABPARPORT;

#define ESCC2	2
#define ESCC8	8

/*
 * Per-chip structure
 */


typedef struct sab_chip 
{
	unsigned int		chip_type;
	struct sab_board	*c_board;	/* Parent board */
	struct aura_cim		*c_cim;		/* if present */
	unsigned char		c_chipno;	/* chip number */
	unsigned char	 	c_revision;	/* the revision code from the VSTR */
	unsigned char         	c_nports;	/* number of ports per chip */
	void 			*c_regs;	/* base address for chip registers */
	struct sab_port		*c_portbase;
	struct sab_chip       	*next;          /* the next chip in the chip chain */
	struct sab_chip       	*next_by_board;    /* the next chip on the board */
	struct sab_chip		*next_by_cim;
	void 			(*int_disable)(struct sab_chip* chip);
} sab_chip_t, SAB_CHIP;


/* Some useful facts */
#define SAB82532_REG_SIZE               0x40
#define SAB82538_REG_SIZE               0x40

/* RFIFO Status Byte */
#define SAB82532_RSTAT_PE		0x80
#define SAB82532_RSTAT_FE		0x40
#define SAB82532_RSTAT_PARITY		0x01

/* Status Register (STAR) */
#define SAB82532_STAR_XDOV		0x80
#define SAB82532_STAR_XFW		0x40
#define SAB82532_STAR_RFNE		0x20
#define SAB82532_STAR_FCS		0x10
#define SAB82532_STAR_TEC		0x08
#define SAB82532_STAR_RLI		0x08
#define SAB82532_STAR_CEC		0x04
#define SAB82532_STAR_CTS		0x02

/* Command Register (CMDR) */
#define SAB82532_CMDR_RMC		0x80
#define SAB82532_CMDR_RRES		0x40
#define SAB82532_CMDR_RHR		0x40
#define SAB82532_CMDR_RFRD		0x20
#define SAB82532_CMDR_STI		0x10
#define SAB82532_CMDR_XF		0x08
#define SAB82532_CMDR_XTF		0x08
#define SAB82532_CMDR_XME		0x02
#define SAB82532_CMDR_XRES		0x01

				/* leaving them for reference */
				/* they are now defined in 8253xioc.h*/
#if 0
/* Mode Register (MODE) */
#define SAB82532_MODE_TM0		0x80
#define SAB82532_MODE_FRTS		0x40
#define SAB82532_MODE_FCTS		0x20
#define SAB82532_MODE_FLON		0x10
#define SAB82532_MODE_TCPU		0x10
#define SAB82532_MODE_RAC		0x08
#define SAB82532_MODE_RTS		0x04
#define SAB82532_MODE_TRS		0x02
#define SAB82532_MODE_TLP		0x01
#endif

/* Receive Status Register (READ)  */
#define SAB82532_RSTA_VFR		0x80
#define SAB82532_RSTA_RDO		0x40
#define SAB82532_RSTA_CRC		0x20
#define SAB82532_RSTA_RAB		0x10

/* Timer Register (TIMR) */
#define SAB82532_TIMR_CNT_MASK		0xe0
#define SAB82532_TIMR_VALUE_MASK	0x1f

/* Data Format (DAFO) */
#define SAB82532_DAFO_XBRK		0x40
#define SAB82532_DAFO_STOP		0x20
#define SAB82532_DAFO_PAR_SPACE		0x00
#define SAB82532_DAFO_PAR_ODD		0x08
#define SAB82532_DAFO_PAR_EVEN		0x10
#define SAB82532_DAFO_PAR_MARK		0x18
#define SAB82532_DAFO_PARE		0x04
#define SAB82532_DAFO_CHL8		0x00
#define SAB82532_DAFO_CHL7		0x01
#define SAB82532_DAFO_CHL6		0x02
#define SAB82532_DAFO_CHL5		0x03

/* RFIFO Control Register (RFC) */
#define SAB82532_RFC_DPS		0x40
#define SAB82532_RFC_DXS		0x20
#define SAB82532_RFC_RFDF		0x10
#define SAB82532_RFC_RFTH_1		0x00
#define SAB82532_RFC_RFTH_4		0x04
#define SAB82532_RFC_RFTH_16		0x08
#define SAB82532_RFC_RFTH_32		0x0c
#define SAB82532_RFC_TCDE		0x01

/* Received Byte Count High (RBCH) */
#define SAB82532_RBCH_DMA		0x80
#define SAB82532_RBCH_CAS		0x20
#define SAB82532_RBCH_OV		0x10
#define SAB82532_RBCH_HMSK		0x0F

/* Transmit Byte Count High (XBCH) */
#define SAB82532_XBCH_DMA		0x80
#define SAB82532_XBCH_CAS		0x20
#define SAB82532_XBCH_XC		0x10

				/* leaving them for reference */
				/* they are now defined in 8253xioc.h*/
#if 0
/* Channel Configuration Register 0 (CCR0) */
#define SAB82532_CCR0_PU		0x80
#define SAB82532_CCR0_MCE		0x40
#define SAB82532_CCR0_SC_NRZ		0x00
#define SAB82532_CCR0_SC_NRZI		0x08
#define SAB82532_CCR0_SC_FM0		0x10
#define SAB82532_CCR0_SC_FM1		0x14
#define SAB82532_CCR0_SC_MANCH		0x18
#define SAB82532_CCR0_SM_HDLC		0x00
#define SAB82532_CCR0_SM_SDLC_LOOP	0x01
#define SAB82532_CCR0_SM_BISYNC		0x02
#define SAB82532_CCR0_SM_ASYNC		0x03

/* Channel Configuration Register 1 (CCR1) */
#define SAB82532_CCR1_SFLG		0x80
#define SAB82532_CCR1_ODS		0x10
#define SAB82532_CCR1_BCR		0x08
#define SAB82532_CCR1_IFF		0x08
#define SAB82532_CCR1_ITF		0x00