8253x.h

这个linux源代码是很全面的~基本完整了~使用c编译的~由于时间问题我没有亲自测试~但就算用来做参考资料也是非常好的

/* -*- linux-c -*- */
/* $Id: 8253x.h,v 1.14 2002/02/10 22:17:25 martillo Exp $
 * sab82532.h: Register Definitions for the Siemens SAB82532 DUSCC
 *
 * Copyright (C) 1997  Eddie C. Dost  ([e-mail])
 *
 * Modified Aug 1, 2000 Francois Wautier  
 * Modified for complete driver Joachim Martillo
 */

/* Modifications:
 * Copyright (C) 2001 By Joachim Martillo, Telford Tools, Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 *
 **/

#ifndef _SAB82532_H
#define _SAB82532_H

#include <linux/types.h>
#include <linux/delay.h>
#include <linux/serial.h>	/* need struct async_icount for ioctl */
#include <linux/netdevice.h>

#include "8253xioc.h"
#include "ring.h"

#define SAB8253X_MAX_TEC_DELAY	200000 /* 1 character time (at 50 baud) */
#define SAB8253X_MAX_CEC_DELAY	 50000 /* 2.5 TX CLKs (at 50 baud) */

#define SERIAL_TYPE_SYNCTTY 3	/* check tty driver to make sure okay */
				/* SERIAL_TYPE_NORMAL and SERIAL_TYPE_CALLOUT */
				/* seem to be used by the tty driver */
				/* only to print out a warning not to */
				/* use callout devices - next version of */
				/* the code, for now want to be able to */
				/* maintain some of the structure of */
				/* a 2.2.* driver for those that are */
				/* running old kernels. */

#define READB(port, rreg) (*port->readbyte)(port,\
	(unsigned char *)&(port->regs->async_read.rreg))
#define WRITEB(port, rreg, val) (*port->writebyte)(port,\
	(unsigned char *)&(port->regs->async_write.rreg), val)
#ifdef DEFINE_VARIABLE
static unsigned char tmpval; 
#endif
	/* Used in the macro below -- don't create a variable called tmpval*/
#define SET_REG_BIT(port,rreg,bit)\
	tmpval=(*port->readbyte)(port,\
		(unsigned char *)&(port->regs->async_read.rreg));\
	tmpval |= bit;\
	(*port->writebyte)(port,\
		(unsigned char *)&(port->regs->async_write.rreg), tmpval);
#define CLEAR_REG_BIT(port,rreg,bit)\
	tmpval=(*port->readbyte)(port,\
		(unsigned char *)&(port->regs->async_read.rreg));\
	tmpval &= ~(bit);\
	(*port->writebyte)(port,\
		(unsigned char *)&(port->regs->async_write.rreg), tmpval);
#define MASK_REG_BIT(port,rreg,bit)\
	tmpval=(*port->readbyte)(port,\
		(unsigned char *)&(port->regs->async_read.rreg));\
	tmpval &= bit;\
	(*port->writebyte)(port,\
		(unsigned char *)&(port->regs->async_write.rreg), tmpval);
#define READ_X_WRITEB(port,rreg,op,val)\
	tmpval=(*port->readbyte)(port,\
		(unsigned char *)&(port->regs->async_read.rreg));\
	tmpval op= val;\
	(*port->writebyte)(port,\
		(unsigned char *)&(port->regs->async_write.rreg), tmpval);


struct sab82532_async_rd_regs 
{
	volatile unsigned char	rfifo[0x20];	/* Receive FIFO				*/
	volatile unsigned char	star;		/* Status Register			*/
	volatile unsigned char	rsta;		/* actually an HDLC register */
	volatile unsigned char	mode;		/* Mode Register			*/
	volatile unsigned char	timr;		/* Timer Register			*/
	volatile unsigned char	xon;		/* XON Character			*/
	volatile unsigned char	xoff;		/* XOFF Character			*/
	volatile unsigned char	tcr;		/* Termination Character Register	*/
	volatile unsigned char	dafo;		/* Data Format				*/
	volatile unsigned char	rfc;		/* RFIFO Control Register		*/
	volatile unsigned char	__pad2;
	volatile unsigned char	rbcl;		/* Receive Byte Count Low		*/
	volatile unsigned char	rbch;		/* Receive Byte Count High		*/
	volatile unsigned char	ccr0;		/* Channel Configuration Register 0	*/
	volatile unsigned char	ccr1;		/* Channel Configuration Register 1	*/
	volatile unsigned char	ccr2;		/* Channel Configuration Register 2	*/
	volatile unsigned char	ccr3;		/* Channel Configuration Register 3	*/
	volatile unsigned char	__pad3[4];
	volatile unsigned char	vstr;		/* Version Status Register		*/
	volatile unsigned char	__pad4[3];
	volatile unsigned char	gis;		/* Global Interrupt Status		*/
	volatile unsigned char	ipc;		/* Interrupt Port Configuration		*/
	volatile unsigned char	isr0;		/* Interrupt Status 0			*/
	volatile unsigned char	isr1;		/* Interrupt Status 1			*/
	volatile unsigned char	pvr;		/* Port Value Register			*/
	volatile unsigned char	pis;		/* Port Interrupt Status		*/
	volatile unsigned char	pcr;		/* Port Configuration Register		*/
	volatile unsigned char	ccr4;		/* Channel Configuration Register 4	*/
};

struct sab82532_async_wr_regs 
{
	unsigned char	xfifo[0x20];	/* Transmit FIFO			*/
	unsigned char	cmdr;		/* Command Register			*/
	unsigned char	__pad1;
	unsigned char	mode;
	unsigned char	timr;
	unsigned char	xon;
	unsigned char	xoff;
	unsigned char	tcr;
	unsigned char	dafo;
	unsigned char	rfc;
	unsigned char	__pad2;
	unsigned char	xbcl;		/* Transmit Byte Count Low		*/
	unsigned char	xbch;		/* Transmit Byte Count High		*/
	unsigned char	ccr0;
	unsigned char	ccr1;
	unsigned char	ccr2;
	unsigned char	ccr3;
	unsigned char	tsax;		/* Time-Slot Assignment Reg. Transmit	*/
	unsigned char	tsar;		/* Time-Slot Assignment Reg. Receive	*/
	unsigned char	xccr;		/* Transmit Channel Capacity Register	*/
	unsigned char	rccr;		/* Receive Channel Capacity Register	*/
	unsigned char	bgr;		/* Baud Rate Generator Register		*/
	unsigned char	tic;		/* Transmit Immediate Character		*/
	unsigned char	mxn;		/* Mask XON Character			*/
	unsigned char	mxf;		/* Mask XOFF Character			*/
	unsigned char	iva;		/* Interrupt Vector Address		*/
	unsigned char	ipc;
	unsigned char	imr0;		/* Interrupt Mask Register 0		*/
	unsigned char	imr1;		/* Interrupt Mask Register 1		*/
	unsigned char	pvr;
	unsigned char	pim;		/* Port Interrupt Mask			*/
	unsigned char	pcr;
	unsigned char	ccr4;
};

struct sab82532_async_rw_regs 
{	/* Read/Write registers			*/
	volatile unsigned char	__pad1[0x20];
	volatile unsigned char	__pad2;
	volatile unsigned char	__pad3;
	volatile unsigned char	mode;
	volatile unsigned char	timr;
	volatile unsigned char	xon;
	volatile unsigned char	xoff;
	volatile unsigned char	tcr;
	volatile unsigned char	dafo;
	volatile unsigned char	rfc;
	volatile unsigned char	__pad4;
	volatile unsigned char	__pad5;
	volatile unsigned char	__pad6;
	volatile unsigned char	ccr0;
	volatile unsigned char	ccr1;
	volatile unsigned char	ccr2;
	volatile unsigned char	ccr3;
	volatile unsigned char	__pad7;
	volatile unsigned char	__pad8;
	volatile unsigned char	__pad9;
	volatile unsigned char	__pad10;
	volatile unsigned char	__pad11;
	volatile unsigned char	__pad12;
	volatile unsigned char	__pad13;
	volatile unsigned char	__pad14;
	volatile unsigned char	__pad15;
	volatile unsigned char	ipc;
	volatile unsigned char	__pad16;
	volatile unsigned char	__pad17;
	volatile unsigned char	pvr;
	volatile unsigned char	__pad18;
	volatile unsigned char	pcr;
	volatile unsigned char	ccr4;
};

union sab82532_async_regs 
{
	__volatile__ struct sab82532_async_rd_regs	r;
	__volatile__ struct sab82532_async_wr_regs	w;
	__volatile__ struct sab82532_async_rw_regs	rw;
};

/* not really used yet */
struct sab82532_hdlc_rd_regs 
{
	volatile unsigned char	rfifo[0x20];	/* Receive FIFO				*/
	volatile unsigned char	star;		/* Status Register			*/
	volatile unsigned char	rsta;
	volatile unsigned char	mode;		/* Mode Register			*/
	volatile unsigned char	timr;		/* Timer Register			*/
	volatile unsigned char	xad1;		/* Tx Address High 1	 		*/
	volatile unsigned char	xad2;		/* Tx Address High 2			*/
	volatile unsigned char	__pad1[2];
	volatile unsigned char	ral1;		/* Rx Address Low 1			*/
	volatile unsigned char	rhcr;		/* Received HDLC Control		*/
	volatile unsigned char	rbcl;		/* Receive Byte Count Low		*/
	volatile unsigned char	rbch;		/* Receive Byte Count High		*/
	volatile unsigned char	ccr0;		/* Channel Configuration Register 0	*/
	volatile unsigned char	ccr1;		/* Channel Configuration Register 1	*/
	volatile unsigned char	ccr2;		/* Channel Configuration Register 2	*/
	volatile unsigned char	ccr3;		/* Channel Configuration Register 3	*/
	volatile unsigned char	__pad2[4];
	volatile unsigned char	vstr;		/* Version Status Register		*/
	volatile unsigned char	__pad3[3];
	volatile unsigned char	gis;		/* Global Interrupt Status		*/
	volatile unsigned char	ipc;		/* Interrupt Port Configuration		*/
	volatile unsigned char	isr0;		/* Interrupt Status 0			*/
	volatile unsigned char	isr1;		/* Interrupt Status 1			*/
	volatile unsigned char	pvr;		/* Port Value Register			*/
	volatile unsigned char	pis;		/* Port Interrupt Status		*/
	volatile unsigned char	pcr;		/* Port Configuration Register		*/
	volatile unsigned char	ccr4;		/* Channel Configuration Register 4	*/
};

struct sab82532_hdlc_wr_regs 
{
	unsigned char	xfifo[0x20];	/* Transmit FIFO			*/
	unsigned char	cmdr;		/* Command Register			*/
	unsigned char	pre;		/* Preamble                             */
	unsigned char	mode;
	unsigned char	timr;
	unsigned char	xad1;		/* Tx Address High 1	 		*/
	unsigned char	xad2;		/* Tx Address High 2	 		*/
	unsigned char	rah1;		/* Rx Address High 1	 		*/
	unsigned char	rah2;		/* Rx Address High 2	 		*/
	unsigned char	ral1;		/* Rx Address Low 1			*/
	unsigned char	ral2;		/* Rx Address Low 2			*/
	unsigned char	xbcl;		/* Transmit Byte Count Low		*/
	unsigned char	xbch;		/* Transmit Byte Count High		*/
	unsigned char	ccr0;
	unsigned char	ccr1;
	unsigned char	ccr2;
	unsigned char	ccr3;
	unsigned char	tsax;		/* Time-Slot Assignment Reg. Transmit	*/
	unsigned char	tsar;		/* Time-Slot Assignment Reg. Receive	*/
	unsigned char	xccr;		/* Transmit Channel Capacity Register	*/
	unsigned char	rccr;		/* Receive Channel Capacity Register	*/
	unsigned char	bgr;		/* Baud Rate Generator Register		*/
	unsigned char	rlcr;		/* Rx Frame Length Check		*/
	unsigned char	aml;		/* Address Mask Low			*/
	unsigned char	amh;		/* Address Mask High			*/
	unsigned char	iva;		/* Interrupt Vector Address		*/
	unsigned char	ipc;
	unsigned char	imr0;		/* Interrupt Mask Register 0		*/
	unsigned char	imr1;		/* Interrupt Mask Register 1		*/
	unsigned char	pvr;
	unsigned char	pim;		/* Port Interrupt Mask			*/
	unsigned char	pcr;
	unsigned char	ccr4;
};

union sab82532_regs 
{
	__volatile__ struct sab82532_async_rd_regs	async_read;
	__volatile__ struct sab82532_async_wr_regs	async_write;
	__volatile__ struct sab82532_hdlc_rd_regs	hdlc_read;
	__volatile__ struct sab82532_hdlc_wr_regs	hdlc_write;
};

/*
 * Modem signal definition
 */

typedef struct mctlsig 
{
	unsigned char *reg;	/* chip register offset */
	unsigned char inverted;	/* interpret the results as inverted */
	unsigned char mask;	/* bit within that register */
	unsigned char val;	/* cached value */
	unsigned int irq;	/* address of correct isr register */
	unsigned char irqmask;	/*  */
	unsigned char cnst;	/* A value that should always be set for
				 * this signal register */ 
} mctlsig_t, MCTLSIG;

union sab8253x_irq_status 
{
	unsigned int stat;
	unsigned char images[4];
	struct
	{
		unsigned char isr0;
		unsigned char isr1;
		unsigned char pis;
	} sreg;
};
				/* the following are deprecated */
				/* older version of structure above */
				/* used array*/
#define      ISR0_IDX 0
#define      ISR1_IDX 1
#define       PIS_IDX 2

/*
 * Each port has a structure like this associated to it.
 * All the port are linked with the  next fields
 * All the port of one chip are linked with the  next_by_chip
 */

#define	FUNCTION_NR	0
#define	FUNCTION_AO	1
#define	FUNCTION_NA	2
#define FUNCTION_UN	3

typedef struct sab_port 
{
	int				magic;
	union sab82532_regs		*regs;
	struct sab_chip			*chip;
	struct sab_board		*board;
	struct tty_struct		*tty;
	unsigned char			*xmit_buf;
	int				 xmit_head; /* put characters on write */
	int				 xmit_tail; /* read from here -- in writeb or writefifo */
	int				 xmit_cnt;
	
	/*
	 * Various linked list pertinent to this link 
	 */
	struct sab_port * next;