aic79xx.reg

这个linux源代码是很全面的~基本完整了~使用c编译的~由于时间问题我没有亲自测试~但就算用来做参考资料也是非常好的

	access_mode	RO
	modes		M_CFG
}

/*
 * SCSI Offset Count
 */
register SOFFCNT {
	address			0x04F
	access_mode	RO
	modes		M_DFF0, M_DFF1, M_SCSI
}

/*
 * LQO Manager Current State
 */
register LQOSTATE {
	address			0x04F
	access_mode	RO
	modes		M_CFG
}

/*
 * LQI Manager Status
 */
register LQISTAT0 {
	address			0x050
	access_mode	RO
	modes		M_DFF0, M_DFF1, M_SCSI
	bit	LQIATNQAS	0x20
	bit	LQICRCT1	0x10
	bit	LQICRCT2	0x08
	bit	LQIBADLQT	0x04
	bit	LQIATNLQ	0x02
	bit	LQIATNCMD	0x01
}

/*
 * Clear LQI Interrupts 0
 */
register CLRLQIINTO {
	address			0x050
	access_mode	WO
	modes		M_DFF0, M_DFF1, M_SCSI
	bit	CLRLQIATNQAS	0x20
	bit	CLRLQICRCT1	0x10
	bit	CLRLQICRCT2	0x08
	bit	CLRLQIBADLQT	0x04
	bit	CLRLQIATNLQ	0x02
	bit	CLRLQIATNCMD	0x01
}

/*
 * LQI Manager Interrupt Mode 0
 */
register LQIMODE0 {
	address			0x050
	access_mode	RW
	modes		M_CFG
	bit	ENLQIATNQASK	0x20
	bit	ENLQICRCT1	0x10
	bit	ENLQICRCT2	0x08
	bit	ENLQIBADLQT	0x04
	bit	ENLQIATNLQ	0x02
	bit	ENLQIATNCMD	0x01
}

/*
 * LQI Manager Status 1
 */
register LQISTAT1 {
	address			0x051
	access_mode	RO
	modes		M_DFF0, M_DFF1, M_SCSI
	mask	LQIPHASE_LQ	0x80
	mask	LQIPHASE_NLQ	0x40
	bit	LQIABORT	0x20
	mask	LQICRCI_LQ	0x10
	mask	LQICRCI_NLQ	0x08
	bit	LQIBADLQI	0x04
	mask	LQIOVERI_LQ	0x02
	mask	LQIOVERI_NLQ	0x01
}

/*
 * Clear LQI Manager Interrupts1
 */
register CLRLQIINT1 {
	address			0x051
	access_mode	WO
	modes		M_DFF0, M_DFF1, M_SCSI
	mask	CLRLQIPHASE_LQ	0x80
	mask	CLRLQIPHASE_NLQ	0x40
	bit	CLRLIQABORT	0x20
	mask	CLRLQICRCI_LQ	0x10
	mask	CLRLQICRCI_NLQ	0x08
	bit	CLRLQIBADLQI	0x04
	mask	CLRLQIOVERI_LQ	0x02
	mask	CLRLQIOVERI_NLQ	0x01
}

/*
 * LQI Manager Interrupt Mode 1
 */
register LQIMODE1 {
	address			0x051
	access_mode	RW
	modes		M_CFG
	mask	ENLQIPHASE_LQ	0x80
	mask	ENLQIPHASE_NLQ	0x40
	bit	ENLIQABORT	0x20
	mask	ENLQICRCI_LQ	0x10
	mask	ENLQICRCI_NLQ	0x08
	bit	ENLQIBADLQI	0x04
	mask	ENLQIOVERI_LQ	0x02
	mask	ENLQIOVERI_NLQ	0x01
}

/*
 * LQI Manager Status 2
 */
register LQISTAT2 {
	address			0x052
	access_mode	RO
	modes		M_DFF0, M_DFF1, M_SCSI
	bit	PACKETIZED	0x80
	bit	LQIPHASE_OUTPKT	0x40
	bit	LQIWORKONLQ	0x20
	bit	LQIWAITFIFO	0x10
	bit	LQISTOPPKT	0x08
	bit	LQISTOPLQ	0x04
	bit	LQISTOPCMD	0x02
	bit	LQIGSAVAIL	0x01
}

/*
 * SCSI Status 3
 */
register SSTAT3 {
	address			0x053
	access_mode	RO
	modes		M_DFF0, M_DFF1, M_SCSI
	bit	NTRAMPERR	0x02
	bit	OSRAMPERR	0x01
}

/*
 * Clear SCSI Status 3
 */
register CLRSINT3 {
	address			0x053
	access_mode	WO
	modes		M_DFF0, M_DFF1, M_SCSI
	bit	CLRNTRAMPERR	0x02
	bit	CLROSRAMPERR	0x01
}

/*
 * SCSI Interrupt Mode 3
 */
register SIMODE3 {
	address			0x053
	access_mode	RW
	modes		M_CFG
	bit	ENNTRAMPERR	0x02
	bit	ENOSRAMPERR	0x01
}

/*
 * LQO Manager Status 0
 */
register LQOSTAT0 {
	address			0x054
	access_mode	RO
	modes		M_DFF0, M_DFF1, M_SCSI
	bit	LQOTARGSCBPERR	0x10
	bit	LQOSTOPT2	0x08
	bit	LQOATNLQ	0x04
	bit	LQOATNPKT	0x02
	bit	LQOTCRC		0x01
}

/*
 * Clear LQO Manager interrupt 0
 */
register CLRLQOINT0 {
	address			0x054
	access_mode	WO
	modes		M_DFF0, M_DFF1, M_SCSI
	bit	CLRLQOTARGSCBPERR	0x10
	bit	CLRLQOSTOPT2		0x08
	bit	CLRLQOATNLQ		0x04
	bit	CLRLQOATNPKT		0x02
	bit	CLRLQOTCRC		0x01
}

/*
 * LQO Manager Interrupt Mode 0
 */
register LQOMODE0 {
	address			0x054
	access_mode	RW
	modes		M_CFG
	bit	ENLQOTARGSCBPERR	0x10
	bit	ENLQOSTOPT2		0x08
	bit	ENLQOATNLQ		0x04
	bit	ENLQOATNPKT		0x02
	bit	ENLQOTCRC		0x01
}

/*
 * LQO Manager Status 1
 */
register LQOSTAT1 {
	address			0x055
	access_mode	RO
	modes		M_DFF0, M_DFF1, M_SCSI
	bit	LQOINITSCBPERR	0x10
	bit	LQOSTOPI2	0x08
	bit	LQOBADQAS	0x04
	bit	LQOBUSFREE	0x02
	bit	LQOPHACHGINPKT	0x01
}

/*
 * Clear LOQ Interrupt 1
 */
register CLRLQOINT1 {
	address			0x055
	access_mode	WO
	modes		M_DFF0, M_DFF1, M_SCSI
	bit	CLRLQOINITSCBPERR	0x10
	bit	CLRLQOSTOPI2		0x08
	bit	CLRLQOBADQAS		0x04
	bit	CLRLQOBUSFREE		0x02
	bit	CLRLQOPHACHGINPKT	0x01
}

/*
 * LQO Manager Interrupt Mode 1
 */
register LQOMODE1 {
	address			0x055
	access_mode	RW
	modes		M_CFG
	bit	ENLQOINITSCBPERR	0x10
	bit	ENLQOSTOPI2		0x08
	bit	ENLQOBADQAS		0x04
	bit	ENLQOBUSFREE		0x02
	bit	ENLQOPHACHGINPKT	0x01
}

/*
 * LQO Manager Status 2
 */
register LQOSTAT2 {
	address			0x056
	access_mode	RO
	modes		M_DFF0, M_DFF1, M_SCSI
	mask	LQOPKT		0xE0
	bit	LQOWAITFIFO	0x10
	bit	LQOPHACHGOUTPKT	0x02	/* outside of packet boundaries. */
	bit	LQOSTOP0	0x01	/* Stopped after sending all packets */
}

/*
 * Output Synchronizer Space Count
 */
register OS_SPACE_CNT {
	address			0x056
	access_mode	RO
	modes		M_CFG
}

/*
 * SCSI Interrupt Mode 1
 * Setting any bit will enable the corresponding function
 * in SIMODE1 to interrupt via the IRQ pin.
 */
register SIMODE1 {
	address			0x057
	access_mode	RW
	modes		M_DFF0, M_DFF1, M_SCSI
	bit	ENSELTIMO	0x80
	bit	ENATNTARG	0x40
	bit	ENSCSIRST	0x20
	bit	ENPHASEMIS	0x10
	bit	ENBUSFREE	0x08
	bit	ENSCSIPERR	0x04
	bit	ENSTRB2FAST	0x02
	bit	ENREQINIT	0x01
}

/*
 * Good Status FIFO
 */
register GSFIFO {
	address			0x058
	access_mode	RO
	size		2
	modes		M_DFF0, M_DFF1, M_SCSI
}

/*
 * Data FIFO SCSI Transfer Control
 */
register DFFSXFRCTL {
	address			0x05A
	access_mode	RW
	modes		M_DFF0, M_DFF1
	bit	CLRSHCNT	0x04
	bit	CLRCHN		0x02
	bit	RSTCHN		0x01
}

/*
 * Next SCSI Control Block
 */
register NEXTSCB {
	address			0x05A
	access_mode	RW
	size		2
	modes		M_SCSI
}
	
/*
 * SEQ Interrupts
 */
register SEQINTSRC {
	address			0x05B
	access_mode	RO
	modes		M_DFF0, M_DFF1
	bit	CTXTDONE	0x40
	bit	SAVEPTRS	0x20
	bit	CFG4DATA	0x10
	bit	CFG4ISTAT	0x08
	bit	CFG4TSTAT	0x04
	bit	CFG4ICMD	0x02
	bit	CFG4TCMD	0x01
}

/*
 * Clear Arp Interrupts
 */
register CLRSEQINTSRC {
	address			0x05B
	access_mode	WO
	modes		M_DFF0, M_DFF1
	bit	CLRCTXTDONE	0x40
	bit	CLRSAVEPTRS	0x20
	bit	CLRCFG4DATA	0x10
	bit	CLRCFG4ISTAT	0x08
	bit	CLRCFG4TSTAT	0x04
	bit	CLRCFG4ICMD	0x02
	bit	CLRCFG4TCMD	0x01
}

/*
 * SEQ Interrupt Enabled (Shared)
 */
register SEQIMODE {
	address			0x05C
	access_mode	RW
	modes		M_DFF0, M_DFF1
	bit	ENCTXTDONE	0x40
	bit	ENSAVEPTRS	0x20
	bit	ENCFG4DATA	0x10
	bit	ENCFG4ISTAT	0x08
	bit	ENCFG4TSTAT	0x04
	bit	ENCFG4ICMD	0x02
	bit	ENCFG4TCMD	0x01
}

/*
 * Current SCSI Control Block
 */
register CURRSCB {
	address			0x05C
	access_mode	RW
	size		2
	modes		M_SCSI
}

/*
 * Data FIFO Status
 */
register MDFFSTAT {
	address			0x05D
	access_mode	RO
	modes		M_DFF0, M_DFF1
	bit	LASTSDONE	0x10
	bit	SHVALID		0x08
	bit	DLZERO		0x04 /* FIFO data ends on packet boundary. */
	bit	DATAINFIFO	0x02
	bit	FIFOFREE	0x01
}

/*
 * CRC Control
 */
register CRCCONTROL {
	address			0x05d
	access_mode	RW
	modes		M_CFG
	bit	CRCVALCHKEN		0x40
}

/*
 * SCSI Test Control
 */
register SCSITEST {
	address			0x05E
	access_mode	RW
	modes		M_CFG
	bit	CNTRTEST	0x08
	bit	SEL_TXPLL_DEBUG	0x04
}

/*
 * Data FIFO Queue Tag
 */
register DFFTAG {
	address			0x05E
	access_mode	RW
	size		2
	modes		M_DFF0, M_DFF1
}

/*
 * Last SCSI Control Block
 */
register LASTSCB {
	address			0x05E
	access_mode	RW
	size		2
	modes		M_SCSI
}

/*
 * SCSI I/O Cell Power-down Control
 */
register IOPDNCTL {
	address			0x05F
	access_mode	RW
	modes		M_CFG
	bit	DISABLE_OE	0x80
	bit	PDN_IDIST	0x04
	bit	PDN_DIFFSENSE	0x01
}

/*
 * Shaddow Host Address.
 */
register SHADDR {
	address			0x060
	access_mode	RO
	size		8
	modes		M_DFF0, M_DFF1
}

/*
 * Data Group CRC Interval.
 */
register DGRPCRCI {
	address			0x060
	access_mode	RW
	size		2
	modes		M_CFG
}

/*
 * Data Transfer Negotiation Address
 */
register NEGOADDR {
	address			0x060
	access_mode	RW
	modes		M_SCSI
}

/*
 * Data Transfer Negotiation Data - Period Byte
 */
register NEGPERIOD {
	address			0x061
	access_mode	RW
	modes		M_SCSI
}

/*
 * Packetized CRC Interval
 */
register PACKCRCI {
	address			0x062
	access_mode	RW
	size		2
	modes		M_CFG
}

/*
 * Data Transfer Negotiation Data - Offset Byte
 */
register NEGOFFSET {
	address			0x062
	access_mode	RW
	modes		M_SCSI
}

/*
 * Data Transfer Negotiation Data - PPR Options
 */
register NEGPPROPTS {
	address			0x063
	access_mode	RW
	modes		M_SCSI
	bit	PPROPT_PACE	0x08
	bit	PPROPT_QAS	0x04
	bit	PPROPT_DT	0x02
	bit	PPROPT_IUT	0x01
}

/*
 * Data Transfer Negotiation Data -  Connection Options
 */
register NEGCONOPTS {
	address			0x064
	access_mode	RW
	modes		M_SCSI
	bit	ENAIP		0x08
	bit	ENAUTOATNI	0x04
	bit	ENAUTOATNO	0x02
	bit	WIDEXFER	0x01
}

/*
 * Negotiation Table Annex Column Index.
 */
register ANNEXCOL {
	address			0x065
	access_mode	RW
	modes		M_SCSI
}

const AHD_ANNEXCOL_PRECOMP	4
const	AHD_PRECOMP_MASK	0x07
const	AHD_PRECOMP_CUTBACK_17	0x04
const	AHD_PRECOMP_CUTBACK_29	0x06
const	AHD_PRECOMP_CUTBACK_37	0x07
const	AHD_PRECOMP_FASTSLEW	0x40
const AHD_NUM_ANNEXCOLS		4

/*
 * Negotiation Table Annex Data Port.
 */
register ANNEXDAT {
	address			0x066
	access_mode	RW
	modes		M_SCSI
}

/*
 * Initiator's Own Id.
 * The SCSI ID to use for Selection Out and seen during a reselection..
 */
register IOWNID {
	address			0x067
	access_mode	RW
	modes		M_SCSI
}

/*
 * 960MHz Phase-Locked Loop Control 0
 */
register PLL960CTL0 {
	address			0x068
	access_mode	RW
	modes		M_CFG
	bit	PLL_VCOSEL	0x80
	bit	PLL_PWDN	0x40
	mask	PLL_NS		0x30
	bit	PLL_ENLUD	0x08
	bit	PLL_ENLPF	0x04
	bit	PLL_DLPF	0x02
	bit	PLL_ENFBM	0x01
}

/*
 * Target Own Id
 */
register TOWNID {
	address			0x069
	access_mode	RW
	modes		M_SCSI
}

/*
 * 960MHz Phase-Locked Loop Control 1
 */
register PLL960CTL1 {
	address			0x069
	access_mode	RW
	modes		M_CFG
	bit	PLL_CNTEN	0x80
	bit	PLL_CNTCLR	0x40
	bit	PLL_RST		0x01
}

/*
 * Expander Signature
 */
register XSIG {
	address			0x06A
	access_mode	RW
	modes		M_SCSI
}

/*
 * Shadow Byte Count
 */
register SHCNT {
	address			0x068
	access_mode	RW
	size		3
	modes		M_DFF0, M_DFF1
}

/*
 * Selection Out ID
 */
register SELOID {
	address			0x06B
	access_mode	RW
	modes		M_SCSI
}

/*
 * 960-MHz Phase-Locked Loop Test Count
 */
register PLL960CNT0 {
	address			0x06A
	access_mode	RO
	size		2
	modes		M_CFG
}

/*
 * 400-MHz Phase-Locked Loop Control 0
 */
register PLL400CTL0 {
	address			0x06C
	access_mode	RW
	modes		M_CFG
	bit	PLL_VCOSEL	0x80
	bit	PLL_PWDN	0x40
	mask	PLL_NS		0x30
	bit	PLL_ENLUD	0x08
	bit	PLL_ENLPF	0x04
	bit	PLL_DLPF	0x02
	bit	PLL_ENFBM	0x01
}

/*
 * Arbitration Fairness
 */
register FAIRNESS {
	address			0x06C
	access_mode	RW
	size		2
	modes		M_SCSI
}

/*
 * 400-MHz Phase-Locked Loop Control 1
 */
register PLL400CTL1 {
	address			0x06D
	access_mode	RW
	modes		M_CFG
	bit	PLL_CNTEN	0x80
	bit	PLL_CNTCLR	0x40
	bit	PLL_RST		0x01
}

/*
 * Arbitration Unfairness
 */
register UNFAIRNESS {
	address			0x06E
	access_mode	RW
	size		2
	modes		M_SCSI
}

/*
 * 400-MHz Phase-Locked Loop Test Count
 */
register PLL400CNT0 {
	address			0x06E
	access_mode	RO
	size		2
	modes		M_CFG
}

/*
 * SCB Page Pointer
 */
register SCBPTR {
	address			0x0A8
	access_mode	RW
	size		2
	modes		M_DFF0, M_DFF1, M_CCHAN, M_SCSI
}

/*
 * CMC SCB Array Count
 * Number of bytes to transfer between CMC SCB memory and SCBRAM.
 * Transfers must be 8byte aligned and sized.
 */
register CCSCBACNT {
	address			0x0AB
	access_mode	RW
	modes		M_CCHAN
}

/*
 * SCB Autopointer
 * SCB-Next Address Snooping logic.  When an SCB is transferred to
 * the card, the next SCB address to be used by the CMC array can
 * be autoloaded from that transfer.
 */
register SCBAUTOPTR {
	address			0x0AB
	access_mode	RW
	modes		M_CFG
	bit	AUSCBPTR_EN	0x80
	mask	SCBPTR_ADDR	0x38
	mask	SCBPTR_OFF	0x07
}

/*
 * CMC SG Ram Address Pointer
 */
register CCSGADDR {
	address			0x0AC
	access_mode	RW
	modes		M_DFF0, M_DFF1
}

/*
 * CMC SCB RAM Address Pointer
 */
register CCSCBADDR {
	address			0x0AC
	access_mode	RW
	modes		M_CCHAN
}

/*
 * CMC SCB Ram Back-up Address Pointer
 * Indicates the true stop location of transfers halted prior
 * to SCBHCNT going to 0.
 */
register CCSCBADR_BK {
	address			0x0AC
	access_mode	RO
	modes		M_CFG
}

/*
 * CMC SG Control
 */
register CCSGCTL {
	address			0x0AD
	access_mode	RW
	modes		M_DFF0, M_DFF1
	bit	CCSGDONE	0x80
	bit	SG_CACHE_AVAIL	0x10
	bit	CCSGEN		0x08
	bit	SG_FETCH_REQ	0x02
	bit	CCSGRESET	0x01
}

/*
 * CMD SCB Control
 */
register CCSCBCTL {
	address			0x0AD
	access_mode	RW
	modes		M_CCHAN
	bit	CCSCBDONE	0x80
	bit	ARRDONE		0x40
	bit	CCARREN		0x10
	bit	CCSCBEN		0x08
	bit	CCSCBDIR	0x04
	bit	CCSCBRESET	0x01
}

/*
 * CMC Ram BIST
 */
register CMC_RAMBIST {
	address			0x0AD
	access_mode	RW
	modes		M_CFG
	bit	SG_ELEMENT_SIZE		0x80
	bit	SCBRAMBIST_FAIL		0x40
	bit	SG_BIST_FAIL		0x20
	bit	SG_BIST_EN		0x10
	bit	CMC_BUFFER_BIST_FAIL	0x02
	bit	CMC_BUFFER_BIST_EN	0x01
}

/*
 * CMC SG RAM Data Port
 */
register CCSGRAM {
	address			0x0B0
	access_mode	RW
	modes		M_DFF0, M_DFF1
}

/*
 * CMC SCB RAM Data Port
 */
register CCSCBRAM {
	address			0x0B0
	access_mode	RW
	modes		M_CCHAN
}

/*
 * Flex DMA Address.
 */
register FLEXADR {
	address			0x0B0
	access_mode	RW
	size		3
	modes		M_SCSI
}

/*
 * Flex DMA Byte Count
 */
register FLEXCNT {
	address			0x0B3
	access_mode	RW
	size		2
	modes		M_SCSI
}

/*
 * Flex DMA Status
 */
register FLEXDMASTAT {
	address			0x0B5
	access_mode	RW
	modes		M_SCSI
	bit	FLEXDMAERR	0x02
	bit	FLEXDMADONE	0x01
}

/*
 * Flex DMA Data Port
 */
register FLEXDATA {
	address			0x0B6
	access_mode	RW
	modes		M_SCSI
}

/*
 * Board Data
 */
register BRDDAT {
	address			0x0B8
	access_mode	RW
	modes		M_SCSI
}

/*
 * Board Control
 */
register BRDCTL {
	address			0x0B9
	access_mode	RW
	modes		M_SCSI
	bit	FLXARBACK	0x80
	bit	FLXARBREQ	0x40
	mask	BRDADDR		0x38
	bit	BRDEN		0x04
	bit	BRDRW		0x02
	bit	BRDSTB		0x01
}

/*
 * Serial EEPROM Address
 */
register SEEADR {
	address			0x0BA
	access_mode	RW
	modes		M_SCSI
}

/*
 * Serial EEPROM Data
 */
register SEEDAT {
	address			0x0BC
	access_mode	RW
	size		2
	modes		M_SCSI
}

/*
 * Serial EEPROM Status
 */
register SEESTAT {
	address			0x0BE
	access_mode	RO
	modes		M_SCSI
	bit	INIT_DONE	0x80
	mask	SEEOPCODE	0x70
	bit	LDALTID_L	0x08
	bit	SEEARBACK	0x04
	bit	SEEBUSY		0x02
	bit	SEESTART	0x01
}

/*
 * Serial EEPROM Control
 */