aic79xx.reg

这个linux源代码是很全面的~基本完整了~使用c编译的~由于时间问题我没有亲自测试~但就算用来做参考资料也是非常好的

/*
 * Aic79xx register and scratch ram definitions.
 *
 * Copyright (c) 1994-2001 Justin T. Gibbs.
 * Copyright (c) 2000-2001 Adaptec Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions, and the following disclaimer,
 *    without modification.
 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
 *    substantially similar to the "NO WARRANTY" disclaimer below
 *    ("Disclaimer") and any redistribution must be conditioned upon
 *    including a substantially similar Disclaimer requirement for further
 *    binary redistribution.
 * 3. Neither the names of the above-listed copyright holders nor the names
 *    of any contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * Alternatively, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") version 2 as published by the Free
 * Software Foundation.
 *
 * NO WARRANTY
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGES.
 *
 * $FreeBSD$
 */
VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#34 $"

/*
 * This file is processed by the aic7xxx_asm utility for use in assembling
 * firmware for the aic79xx family of SCSI host adapters as well as to generate
 * a C header file for use in the kernel portion of the Aic79xx driver.
 */

/* Register window Modes */
#define M_DFF0		0
#define M_DFF1		1
#define M_CCHAN		2
#define M_SCSI		3
#define M_CFG		4
#define M_DST_SHIFT	4

#define MK_MODE(src, dst) ((src) | ((dst) << M_DST_SHIFT))
#define SET_MODE(src, dst)					\
	SET_SRC_MODE	src;					\
	SET_DST_MODE	dst;					\
	mvi	MK_MODE(src, dst) call set_mode_work_around

/*
 * Mode Pointer
 * Controls which of the 5, 512byte, address spaces should be used
 * as the source and destination of any register accesses in our
 * register window.
 */
register MODE_PTR {
	address			0x000
	access_mode	RW
	mask	DST_MODE	0x70
	mask	SRC_MODE	0x07
	mode_pointer
}

const SRC_MODE_SHIFT	0
const DST_MODE_SHIFT	4

/*
 * Host Interrupt Status
 */
register INTSTAT {
	address			0x001
	access_mode	RW
	bit	HWERRINT	0x80
	bit	BRKADRINT	0x40
	bit	SWTMINT		0x20
	bit	PCIINT		0x10
	bit	SCSIINT		0x08
	bit	SEQINT		0x04
	bit	CMDCMPLT	0x02
	bit	SPLTINT		0x01
	mask	INT_PEND 0xFF
}

/*
 * Sequencer Interrupt Code
 */
register SEQINTCODE {
	address			0x002
	access_mode	RW
	mask	BAD_PHASE	1		/* unknown scsi bus phase */
	mask	SEND_REJECT	2		/* sending a message reject */
	mask	PROTO_VIOLATION 3		/* Protocol Violation */
	mask	NO_MATCH	4		/* no cmd match for reconnect */
	mask	IGN_WIDE_RES	5		/* Complex IGN Wide Res Msg */
	mask	PDATA_REINIT	6		/*
						 * Returned to data phase
						 * that requires data
						 * transfer pointers to be
						 * recalculated from the
						 * transfer residual.
						 */
	mask	HOST_MSG_LOOP	7		/*
						 * The bus is ready for the
						 * host to perform another
						 * message transaction.  This
						 * mechanism is used for things
						 * like sync/wide negotiation
						 * that require a kernel based
						 * message state engine.
						 */
	mask	BAD_STATUS	8		/* Bad status from target */
	mask	DATA_OVERRUN	9		/*
						 * Target attempted to write
						 * beyond the bounds of its
						 * command.
						 */
	mask	MKMSG_FAILED	10		/*
						 * Target completed command
						 * without honoring our ATN
						 * request to issue a message. 
						 */
	mask	MISSED_BUSFREE	11		/*
						 * The sequencer never saw
						 * the bus go free after
						 * either a command complete
						 * or disconnect message.
						 */
	mask	SCB_MISMATCH	12		/*
						 * Downloaded SCB's tag does
						 * not match the entry we
						 * intended to download.
						 */
	mask	NO_FREE_SCB	13		/*
						 * get_free_or_disc_scb failed.
						 */
	mask	OUT_OF_RANGE	14
	mask	NO_FREE_FIFO	15
	mask	DUMP_CARD_STATE	16
	mask	ILLEGAL_PHASE	17
	mask	INVALID_SEQINT	18
	mask	CFG4ISTAT_INTR	19
	mask	STATUS_OVERRUN	20
	mask	CFG4OVERRUN	21
	mask	SNAPSHOTCLRCHN	22
	mask	MONITORDRAIN	23
	mask	ENTERING_NONPACK 24
	mask	PCIX_ARBITOR_WW 25
}

/*
 * Clear Host Interrupt
 */
register CLRINT {
	address			0x003
	access_mode	WO
	bit	CLRBRKADRINT	0x40
	bit	CLRSWTMINT	0x20
	bit	CLRSCSIINT	0x08
	bit	CLRSEQINT	0x04
	bit	CLRCMDINT	0x02
	bit	CLRSPLTINT	0x01
}

/*
 * Error Register
 */
register ERROR {
	address			0x004
	access_mode	RO
	bit	CIOPARERR	0x80
	bit	MPARERR		0x20
	bit	DPARERR		0x10
	bit	SQPARERR	0x08
	bit	ILLOPCODE	0x04
	bit	DSCTMOUT	0x02
}

/*
 * Clear Error
 */
register CLRERR {
	address			0x004
	access_mode 	WO
	bit	CLRCIOPARERR	0x80
	bit	CLRMPARERR	0x20
	bit	CLRDPARERR	0x10
	bit	CLRSQPARERR	0x08
	bit	CLRILLOPCODE	0x04
	bit	CLRDSCTMOUT	0x02
}

/*
 * Host Control Register
 * Overall host control of the device.
 */
register HCNTRL {
	address			0x005
	access_mode	RW
	bit	POWRDN		0x40
	bit	SWINT		0x10
	bit	HCNTRL3		0x08
	bit	PAUSE		0x04
	bit	INTEN		0x02
	bit	CHIPRST		0x01
	bit	CHIPRSTACK	0x01
}

/*
 * Host New SCB Queue Offset
 */
register HNSCB_QOFF {
	address			0x006
	access_mode	RW
	size		2
}

/*
 * Host Empty SCB Queue Offset
 */
register HESCB_QOFF {
	address			0x008
	access_mode	RW
}

/*
 * Host Mailbox
 */
register HS_MAILBOX {
	address			0x0B
	access_mode	RW
	mask	HOST_TQINPOS	0x80	/* Boundary at either 0 or 128 */
}

/*
 * Sequencer Interupt Status
 */
register SEQINTSTAT {
	address			0x0C
	access_mode	RO
	bit	SEQ_SWTMRTO	0x10
	bit	SEQ_SEQINT	0x08
	bit	SEQ_SCSIINT	0x04
	bit	SEQ_PCIINT	0x02
	bit	SEQ_SPLTINT	0x01
}

/*
 * Clear SEQ Interrupt
 */
register CLRSEQINTSTAT {
	address			0x0C0
	access_mode	WO
	bit	CLRSEQ_SWTMRTO	0x10
	bit	CLRSEQ_SEQINT	0x08
	bit	CLRSEQ_SCSIINT	0x04
	bit	CLRSEQ_PCIINT	0x02
	bit	CLRSEQ_SPLTINT	0x01
}

/*
 * Software Timer
 */
register SWTIMER {
	address			0x0E0
	access_mode	RW
	size		2
}

/*
 * SEQ New SCB Queue Offset
 */
register SNSCB_QOFF {
	address			0x010
	access_mode	RW
	size		2
	modes		M_CCHAN
}

/*
 * SEQ Empty SCB Queue Offset
 */
register SESCB_QOFF {
	address			0x012
	access_mode	RW
	modes		M_CCHAN
}

/*
 * SEQ Done SCB Queue Offset
 */
register SDSCB_QOFF {
	address			0x014
	access_mode	RW
	modes		M_CCHAN
	size		2
}

/*
 * Queue Offset Control & Status
 */
register QOFF_CTLSTA {
	address			0x016
	access_mode	RW
	modes		M_CCHAN
	bit	EMPTY_SCB_AVAIL	0x80
	bit	NEW_SCB_AVAIL	0x40
	bit	SDSCB_ROLLOVR	0x20
	bit	HS_MAILBOX_ACT	0x10
	mask	SCB_QSIZE	0x0F
	mask	SCB_QSIZE_4	0x00
	mask	SCB_QSIZE_8	0x01
	mask	SCB_QSIZE_16	0x02
	mask	SCB_QSIZE_32	0x03
	mask	SCB_QSIZE_64	0x04
	mask	SCB_QSIZE_128	0x05
	mask	SCB_QSIZE_256	0x06
	mask	SCB_QSIZE_512	0x07
	mask	SCB_QSIZE_1024	0x08
	mask	SCB_QSIZE_2048	0x09
	mask	SCB_QSIZE_4096	0x0A
	mask	SCB_QSIZE_8192	0x0B
	mask	SCB_QSIZE_16384	0x0C
}

/*
 * Interrupt Control
 */
register INTCTL {
	address			0x018
	access_mode	RW
	bit	SWTMINTMASK	0x80
	bit	SWTMINTEN	0x40
	bit	SWTIMER_START	0x20
	bit	AUTOCLRCMDINT	0x10
	bit	PCIINTEN	0x08
	bit	SCSIINTEN	0x04
	bit	SEQINTEN	0x02
	bit	SPLTINTEN	0x01
}

/*
 * Data FIFO Control
 */
register DFCNTRL {
	address			0x019
	access_mode	RW
	modes		M_DFF0, M_DFF1
	bit	PRELOADEN	0x80
	bit	SCSIEN		0x20
	bit	SCSIENACK	0x20
	bit	HDMAEN		0x08
	bit	HDMAENACK	0x08
	bit	DIRECTION	0x04
	bit	DIRECTIONACK	0x04
	bit	FIFOFLUSH	0x02
	bit	FIFOFLUSHACK	0x02
	bit	DIRECTIONEN	0x01
}

/*
 * Device Space Command 0
 */
register DSCOMMAND0 {
	address			0x019
	access_mode	RW
	modes		M_CFG
	bit	CACHETHEN	0x80	/* Cache Threshold enable */
	bit	DPARCKEN	0x40	/* Data Parity Check Enable */
	bit	MPARCKEN	0x20	/* Memory Parity Check Enable */
	bit	EXTREQLCK	0x10	/* External Request Lock */
	bit	CIOPARCKEN	0x01	/* Internal bus parity error enable */
}

/*
 * Data FIFO Status
 */
register DFSTATUS {
	address			0x01A
	access_mode	RO
	modes		M_DFF0, M_DFF1
	bit	PRELOAD_AVAIL		0x80
	bit	PKT_PRELOAD_AVAIL	0x40
	bit	MREQPEND		0x10
	bit	HDONE			0x08
	bit	DFTHRESH		0x04
	bit	FIFOFULL		0x02
	bit	FIFOEMP			0x01
}

/*
 * S/G Cache Pointer
 */
register SG_CACHE_PRE {
	address			0x01B
	access_mode	WO
	modes		M_DFF0, M_DFF1
	mask	SG_ADDR_MASK	0xf8
	bit	ODD_SEG		0x04
	bit	LAST_SEG	0x02
}

register SG_CACHE_SHADOW {
	address			0x01B
	access_mode	RO
	modes		M_DFF0, M_DFF1
	mask	SG_ADDR_MASK	0xf8
	bit	ODD_SEG		0x04
	bit	LAST_SEG	0x02
	bit	LAST_SEG_DONE	0x01
}

/*
 * Arbiter Control
 */
register ARBCTL {
	address			0x01B
	access_mode	RW
	modes		M_CFG
	bit	RESET_HARB	0x80
	bit	RETRY_SWEN	0x08
	mask	USE_TIME	0x07
}

/*
 * Data Channel Host Address
 */
register HADDR {
	address			0x070
	access_mode	RW
	size		8
	modes		M_DFF0, M_DFF1
}

/*
 * Host Overlay DMA Address
 */
register HODMAADR {
	address			0x070
	access_mode	RW
	size		8
	modes		M_SCSI
}

/*
 * Data Channel Host Count
 */
register HCNT {
	address			0x078
	access_mode	RW
	size		3
	modes		M_DFF0, M_DFF1
}

/*
 * Host Overlay DMA Count
 */
register HODMACNT {
	address			0x078
	access_mode	RW
	size		2
	modes		M_SCSI
}

/*
 * Host Overlay DMA Enable
 */
register HODMAEN {
	address			0x07A
	access_mode	RW
	modes		M_SCSI
}

/*
 * Scatter/Gather Host Address
 */
register SGHADDR {
	address			0x07C
	access_mode	RW
	size		8
	modes		M_DFF0, M_DFF1
}

/*
 * SCB Host Address
 */
register SCBHADDR {
	address			0x07C
	access_mode	RW
	size		8
	modes		M_CCHAN
}

/*
 * Scatter/Gather Host Count
 */
register SGHCNT {
	address			0x084
	access_mode	RW
	modes		M_DFF0, M_DFF1
}

/*
 * SCB Host Count
 */
register SCBHCNT {
	address			0x084
	access_mode	RW
	modes		M_CCHAN
}

/*
 * Data FIFO Threshold
 */
register DFF_THRSH {
	address			0x088
	access_mode	RW
	modes		M_CFG
	mask	WR_DFTHRSH	0x70
	mask	RD_DFTHRSH	0x07
	mask	RD_DFTHRSH_MIN	0x00
	mask	RD_DFTHRSH_25	0x01
	mask	RD_DFTHRSH_50	0x02
	mask	RD_DFTHRSH_63	0x03
	mask	RD_DFTHRSH_75	0x04
	mask	RD_DFTHRSH_85	0x05
	mask	RD_DFTHRSH_90	0x06
	mask	RD_DFTHRSH_MAX	0x07
	mask	WR_DFTHRSH_MIN	0x00
	mask	WR_DFTHRSH_25	0x10
	mask	WR_DFTHRSH_50	0x20
	mask	WR_DFTHRSH_63	0x30
	mask	WR_DFTHRSH_75	0x40
	mask	WR_DFTHRSH_85	0x50
	mask	WR_DFTHRSH_90	0x60
	mask	WR_DFTHRSH_MAX	0x70
}

/*
 * ROM Address
 */
register ROMADDR {
	address			0x08A
	access_mode	RW
	size		3
}

/*
 * ROM Control
 */
register ROMCNTRL {
	address			0x08D
	access_mode	RW
	mask	ROMOP		0xE0
	mask	ROMSPD		0x18
	bit	REPEAT		0x02
	bit	RDY		0x01
}

/*
 * ROM Data
 */
register ROMDATA {
	address			0x08E
	access_mode	RW
}

/*
 * Data Channel Receive Message 0
 */
register DCHRXMSG0 {
	address			0x090
	access_mode	RO
	modes		M_DFF0, M_DFF1
	mask		CDNUM	0xF8
	mask		CFNUM	0x07
}

/*
 * CMC Recieve Message 0
 */
register CMCRXMSG0 {
	address			0x090
	access_mode	RO
	modes		M_CCHAN
	mask		CDNUM	0xF8
	mask		CFNUM	0x07
}

/*
 * Overlay Recieve Message 0
 */
register OVLYRXMSG0 {
	address			0x090
	access_mode	RO
	modes		M_SCSI
	mask		CDNUM	0xF8
	mask		CFNUM	0x07
}

/*
 * Relaxed Order Enable
 */
register ROENABLE {
	address			0x090
	access_mode	RW
	modes		M_CFG
	bit	MSIROEN		0x20
	bit	OVLYROEN	0x10
	bit	CMCROEN		0x08
	bit	SGROEN		0x04
	bit	DCH1ROEN	0x02
	bit	DCH0ROEN	0x01
}

/*
 * Data Channel Receive Message 1
 */
register DCHRXMSG1 {
	address			0x091
	access_mode	RO
	modes		M_DFF0, M_DFF1
	mask	CBNUM		0xFF
}

/*
 * CMC Recieve Message 1
 */
register CMCRXMSG1 {
	address			0x091
	access_mode	RO
	modes		M_CCHAN
	mask	CBNUM		0xFF
}

/*
 * Overlay Recieve Message 1
 */
register OVLYRXMSG1 {
	address			0x091
	access_mode	RO
	modes		M_SCSI
	mask	CBNUM		0xFF
}

/*
 * No Snoop Enable
 */
register NSENABLE {
	address			0x091
	access_mode	RW
	modes		M_CFG
	bit	MSINSEN		0x20
	bit	OVLYNSEN	0x10
	bit	CMCNSEN		0x08
	bit	SGNSEN		0x04
	bit	DCH1NSEN	0x02
	bit	DCH0NSEN	0x01
}

/*
 * Data Channel Receive Message 2
 */
register DCHRXMSG2 {
	address			0x092
	access_mode	RO
	modes		M_DFF0, M_DFF1
	mask	MINDEX		0xFF
}

/*
 * CMC Recieve Message 2
 */
register CMCRXMSG2 {
	address			0x092
	access_mode	RO
	modes		M_CCHAN
	mask	MINDEX		0xFF
}

/*
 * Overlay Recieve Message 2
 */
register OVLYRXMSG2 {
	address			0x092
	access_mode	RO
	modes		M_SCSI
	mask	MINDEX		0xFF
}

/*
 * Outstanding Split Transactions
 */
register OST {
	address			0x092
	access_mode	RW
	modes		M_CFG
}

/*
 * Data Channel Receive Message 3
 */
register DCHRXMSG3 {
	address			0x093
	access_mode	RO
	modes		M_DFF0, M_DFF1
	mask	MCLASS		0x0F
}

/*
 * CMC Recieve Message 3
 */
register CMCRXMSG3 {
	address			0x093
	access_mode	RO
	modes		M_CCHAN
	mask	MCLASS		0x0F
}

/*
 * Overlay Recieve Message 3
 */
register OVLYRXMSG3 {
	address			0x093
	access_mode	RO
	modes		M_SCSI
	mask	MCLASS		0x0F
}

/*
 * PCI-X Control
 */
register PCIXCTL {
	address			0x093
	access_mode	RW
	modes		M_CFG
	bit	SERRPULSE	0x80
	bit	UNEXPSCIEN	0x20
	bit	SPLTSMADIS	0x10
	bit	SPLTSTADIS	0x08
	bit	SRSPDPEEN	0x04
	bit	TSCSERREN	0x02
	bit	CMPABCDIS	0x01
}

/*
 * CMC Sequencer Byte Count
 */
register CMCSEQBCNT {
	address			0x094
	access_mode	RO
	modes		M_CCHAN
}

/*
 * Overlay Sequencer Byte Count
 */
register OVLYSEQBCNT {
	address			0x094
	access_mode	RO
	modes		M_SCSI
}

/*
 * Data Channel Sequencer Byte Count
 */
register DCHSEQBCNT {
	address			0x094
	access_mode	RO
	size		2
	modes		M_DFF0, M_DFF1
}

/*
 * Data Channel Split Status 0
 */
register DCHSPLTSTAT0 {
	address			0x096
	access_mode	RW
	modes		M_DFF0, M_DFF1
	bit	STAETERM	0x80
	bit	SCBCERR		0x40
	bit	SCADERR		0x20
	bit	SCDATBUCKET	0x10
	bit	CNTNOTCMPLT	0x08
	bit	RXOVRUN		0x04
	bit	RXSCEMSG	0x02
	bit	RXSPLTRSP	0x01
}

/*
 * CMC Split Status 0
 */
register CMCSPLTSTAT0 {
	address			0x096
	access_mode	RW
	modes		M_CCHAN
	bit	STAETERM	0x80
	bit	SCBCERR		0x40
	bit	SCADERR		0x20
	bit	SCDATBUCKET	0x10
	bit	CNTNOTCMPLT	0x08
	bit	RXOVRUN		0x04
	bit	RXSCEMSG	0x02
	bit	RXSPLTRSP	0x01
}

/*
 * Overlay Split Status 0
 */
register OVLYSPLTSTAT0 {
	address			0x096
	access_mode	RW
	modes		M_SCSI
	bit	STAETERM	0x80
	bit	SCBCERR		0x40
	bit	SCADERR		0x20
	bit	SCDATBUCKET	0x10
	bit	CNTNOTCMPLT	0x08
	bit	RXOVRUN		0x04
	bit	RXSCEMSG	0x02
	bit	RXSPLTRSP	0x01
}

/*
 * Data Channel Split Status 1
 */
register DCHSPLTSTAT1 {
	address			0x097
	access_mode	RW
	modes		M_DFF0, M_DFF1
	bit	RXDATABUCKET	0x01
}

/*
 * CMC Split Status 1
 */
register CMCSPLTSTAT1 {
	address			0x097
	access_mode	RW
	modes		M_CCHAN
	bit	RXDATABUCKET	0x01
}

/*
 * Overlay Split Status 1
 */
register OVLYSPLTSTAT1 {
	address			0x097
	access_mode	RW
	modes		M_SCSI
	bit	RXDATABUCKET	0x01
}

/*
 * S/G Receive Message 0
 */
register SGRXMSG0 {
	address			0x098
	access_mode	RO
	modes		M_DFF0, M_DFF1
	mask		CDNUM	0xF8
	mask		CFNUM	0x07
}

/*
 * S/G Receive Message 1
 */
register SGRXMSG1 {
	address			0x099
	access_mode	RO
	modes		M_DFF0, M_DFF1
	mask	CBNUM		0xFF
}

/*
 * S/G Receive Message 2
 */
register SGRXMSG2 {
	address			0x09A
	access_mode	RO
	modes		M_DFF0, M_DFF1
	mask	MINDEX		0xFF
}

/*
 * S/G Receive Message 3
 */
register SGRXMSG3 {
	address			0x09B
	access_mode	RO
	modes		M_DFF0, M_DFF1
	mask	MCLASS		0x0F
}

/*
 * Slave Split Out Address 0
 */
register SLVSPLTOUTADR0 {
	address			0x098
	access_mode	RO
	modes		M_SCSI
	mask	LOWER_ADDR	0x7F
}

/*
 * Slave Split Out Address 1
 */
register SLVSPLTOUTADR1 {
	address			0x099
	access_mode	RO
	modes		M_SCSI
	mask	REQ_DNUM	0xF8
	mask	REQ_FNUM	0x07
}

/*