aic79xx.h

这个linux源代码是很全面的~基本完整了~使用c编译的~由于时间问题我没有亲自测试~但就算用来做参考资料也是非常好的

/*
 * Core definitions and data structures shareable across OS platforms.
 *
 * Copyright (c) 1994-2001 Justin T. Gibbs.
 * Copyright (c) 2000-2001 Adaptec Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions, and the following disclaimer,
 *    without modification.
 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
 *    substantially similar to the "NO WARRANTY" disclaimer below
 *    ("Disclaimer") and any redistribution must be conditioned upon
 *    including a substantially similar Disclaimer requirement for further
 *    binary redistribution.
 * 3. Neither the names of the above-listed copyright holders nor the names
 *    of any contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * Alternatively, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") version 2 as published by the Free
 * Software Foundation.
 *
 * NO WARRANTY
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGES.
 *
 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.h#46 $
 *
 * $FreeBSD$
 */

#ifndef _AIC79XX_H_
#define _AIC79XX_H_

/* Register Definitions */
#include "aic79xx_reg.h"

/************************* Forward Declarations *******************************/
struct ahd_platform_data;
struct scb_platform_data;

/****************************** Useful Macros *********************************/
#ifndef MAX
#define MAX(a,b) (((a) > (b)) ? (a) : (b))
#endif

#ifndef MIN
#define MIN(a,b) (((a) < (b)) ? (a) : (b))
#endif

#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif

#define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array))

#define ALL_CHANNELS '\0'
#define ALL_TARGETS_MASK 0xFFFF
#define INITIATOR_WILDCARD	(~0)
#define	SCB_LIST_NULL		0xFF00
#define	SCB_LIST_NULL_LE	(ahd_htole16(SCB_LIST_NULL))
#define SCBID_IS_NULL(scbid) (((scbid) & 0xFF00 ) == SCB_LIST_NULL)

#define SCSIID_TARGET(ahd, scsiid)	\
	(((scsiid) & TID) >> TID_SHIFT)
#define SCSIID_OUR_ID(scsiid)		\
	((scsiid) & OID)
#define SCSIID_CHANNEL(ahd, scsiid) ('A')
#define	SCB_IS_SCSIBUS_B(ahd, scb) (0)
#define	SCB_GET_OUR_ID(scb) \
	SCSIID_OUR_ID((scb)->hscb->scsiid)
#define	SCB_GET_TARGET(ahd, scb) \
	SCSIID_TARGET((ahd), (scb)->hscb->scsiid)
#define	SCB_GET_CHANNEL(ahd, scb) \
	SCSIID_CHANNEL(ahd, (scb)->hscb->scsiid)
#define	SCB_GET_LUN(scb) \
	((scb)->hscb->lun)
#define SCB_GET_TARGET_OFFSET(ahd, scb)	\
	SCB_GET_TARGET(ahd, scb)
#define SCB_GET_TARGET_MASK(ahd, scb) \
	(0x01 << (SCB_GET_TARGET_OFFSET(ahd, scb)))
/*
 * TCLs have the following format: TTTTLLLLLLLL
 */
#define TCL_TARGET_OFFSET(tcl) \
	((((tcl) >> 4) & TID) >> 4)
#define TCL_LUN(tcl) \
	(tcl & (AHD_NUM_LUNS_NONPKT - 1))
#define BUILD_TCL(scsiid, lun) \
	((lun) | (((scsiid) & TID) << 4))
#define BUILD_TCL_RAW(target, channel, lun) \
	((lun) | ((target) << 8))

#define SCB_GET_TAG(scb) \
	ahd_le16toh(scb->hscb->tag)

#ifndef	AHD_TARGET_MODE
#undef	AHD_TMODE_ENABLE
#define	AHD_TMODE_ENABLE 0
#endif

/**************************** Driver Constants ********************************/
/*
 * The maximum number of supported targets.
 */
#define AHD_NUM_TARGETS 16

/*
 * The maximum number of supported luns.
 * The identify message only supports 64 luns in non-packetized transfers.
 * You can have 2^64 luns when information unit transfers are enabled,
 * but until we see a need to support that many, we support 256.
 */
#define AHD_NUM_LUNS_NONPKT 64
#define AHD_NUM_LUNS 256

/*
 * The maximum transfer per S/G segment.
 */
#define AHD_MAXTRANSFER_SIZE	 0x00ffffff	/* limited by 24bit counter */

/*
 * The maximum amount of SCB storage in hardware on a controller.
 * This value represents an upper bound.  Due to software design,
 * we may not be able to use this number.
 */
#define AHD_SCB_MAX	512

/*
 * The maximum number of concurrent transactions supported per driver instance.
 * Sequencer Control Blocks (SCBs) store per-transaction information.
 * We are limited to 510 because:
 * 	1) SCB storage space holds us to at most 512.
 *	2) Our input queue scheme requires one SCB to always be reserved
 *	   in advance of queuing any SCBs.  This takes us down to 511.
 *	3) To handle our output queue correctly on machines that only
 * 	   support 32bit stores, we must clear the array 4 bytes at a
 *	   time.  To avoid colliding with a DMA write from the sequencer,
 *	   we must be sure that 2, 16bit slots are empty when we write to
 * 	   clear the queue.  This restricts us to only 511 SCBs: 1 that
 *	   just completed and the known additional empty slot in the queue
 *	   that precedes it.
#define AHD_MAX_QUEUE	510
 */
#define AHD_MAX_QUEUE	255

/*
 * Define the size of our QIN and QOUT FIFOs.  They must be a power of 2
 * in size and accomodate as many transactions as can be queued concurrently.
 */
#define	AHD_QIN_SIZE	512
#define	AHD_QOUT_SIZE	512

#define AHD_QIN_WRAP(x) ((x) & (AHD_QIN_SIZE-1))
#define AHD_QOUT_WRAP(x) ((x) & (AHD_QOUT_SIZE-1))

/*
 * The maximum amount of SCB storage we allocate in host memory.  This
 * number should reflect the 1 additional SCB we require to handle our
 * qinfifo mechanism.
 */
#define AHD_SCB_MAX_ALLOC (AHD_MAX_QUEUE+1)

/*
 * Ring Buffer of incoming target commands.
 * We allocate 256 to simplify the logic in the sequencer
 * by using the natural wrap point of an 8bit counter.
 */
#define AHD_TMODE_CMDS	256

/* Reset line assertion time in us */
#define AHD_BUSRESET_DELAY	250

/******************* Chip Characteristics/Operating Settings  *****************/
/*
 * Chip Type
 * The chip order is from least sophisticated to most sophisticated.
 */
typedef enum {
	AHD_NONE	= 0x0000,
	AHD_CHIPID_MASK	= 0x00FF,
	AHD_AIC7901	= 0x0001,
	AHD_AIC7902	= 0x0002,
	AHD_PCI		= 0x0100,	/* Bus type PCI */
	AHD_PCIX	= 0x0200,	/* Bus type PCIX */
	AHD_BUS_MASK	= 0x0F00
} ahd_chip;

/*
 * Features available in each chip type.
 */
typedef enum {
	AHD_FENONE	= 0x00000,
	AHD_WIDE  	= 0x00001,	/* Wide Channel */
	AHD_MULTI_FUNC	= 0x00100,	/* Multi-Function Twin Channel Device */
	AHD_TARGETMODE	= 0x01000,	/* Has tested target mode support */
	AHD_MULTIROLE	= 0x02000,	/* Space for two roles at a time */
	AHD_REMOVABLE	= 0x00000,	/* Hot-Swap supported - None so far*/
	AHD_AIC7901_FE	= AHD_FENONE,
	AHD_AIC7902_FE	= AHD_MULTI_FUNC
} ahd_feature;

/*
 * Bugs in the silicon that we work around in software.
 */
typedef enum {
	AHD_BUGNONE		= 0x0000,
	AHD_SENT_SCB_UPDATE_BUG	= 0x0001,
	AHD_ABORT_LQI_BUG	= 0x0002,
	AHD_PKT_BITBUCKET_BUG	= 0x0004,
	AHD_LONG_SETIMO_BUG	= 0x0008,
	AHD_NLQICRC_DELAYED_BUG	= 0x0010,
	AHD_SCSIRST_BUG		= 0x0020,
	AHD_PCIX_ARBITER_BUG	= 0x0040,
	AHD_PCIX_SPLIT_BUG	= 0x0080,
	AHD_PCIX_CHIPRST_BUG	= 0x0100,
	AHD_PCIX_MMAPIO_BUG	= 0x0200,
	/* Bug workarounds that can be disabled on non-PCIX busses. */
	AHD_PCIX_BUG_MASK	= AHD_PCIX_ARBITER_BUG
				| AHD_PCIX_SPLIT_BUG
				| AHD_PCIX_CHIPRST_BUG
				| AHD_PCIX_MMAPIO_BUG,
	AHD_LQO_ATNO_BUG	= 0x0400,
	AHD_AUTOFLUSH_BUG	= 0x0800,
	AHD_CLRLQO_AUTOCLR_BUG	= 0x1000,
	AHD_PKTIZED_STATUS_BUG  = 0x2000
} ahd_bug;

/*
 * Configuration specific settings.
 * The driver determines these settings by probing the
 * chip/controller's configuration.
 */
typedef enum {
	AHD_FNONE	      = 0x00000,
	AHD_PRIMARY_CHANNEL   = 0x00003,/*
					 * The channel that should
					 * be probed first.
					 */
	AHD_USEDEFAULTS	      = 0x00004,/*
					 * For cards without an seeprom
					 * or a BIOS to initialize the chip's
					 * SRAM, we use the default target
					 * settings.
					 */
	AHD_SEQUENCER_DEBUG   = 0x00008,
	AHD_RESET_BUS_A	      = 0x00010,
	AHD_EXTENDED_TRANS_A  = 0x00020,
	AHD_TERM_ENB_A	      = 0x00040,
	AHD_SPCHK_ENB_A	      = 0x00080,
	AHD_STPWLEVEL_A	      = 0x00100,
	AHD_INITIATORROLE     = 0x00200,/*
					 * Allow initiator operations on
					 * this controller.
					 */
	AHD_TARGETROLE	      = 0x00400,/*
					 * Allow target operations on this
					 * controller.
					 */
	AHD_RESOURCE_SHORTAGE = 0x00800,
	AHD_TQINFIFO_BLOCKED  = 0x01000,/* Blocked waiting for ATIOs */
	AHD_INT50_SPEEDFLEX   = 0x02000,/*
					 * Internal 50pin connector
					 * sits behind an aic3860
					 */
	AHD_BIOS_ENABLED      = 0x04000,
	AHD_ALL_INTERRUPTS    = 0x08000,
	AHD_39BIT_ADDRESSING  = 0x10000,/* Use 39 bit addressing scheme. */
	AHD_64BIT_ADDRESSING  = 0x20000,/* Use 64 bit addressing scheme. */
	AHD_CURRENT_SENSING   = 0x40000,
	AHD_SCB_CONFIG_USED   = 0x80000,/* No SEEPROM but SCB had info. */
	AHD_CPQ_BOARD	      = 0x100000
} ahd_flag;

/************************* Hardware  SCB Definition ***************************/

/*
 * The driver keeps up to MAX_SCB scb structures per card in memory.  The SCB
 * consists of a "hardware SCB" mirroring the fields availible on the card
 * and additional information the kernel stores for each transaction.
 *
 * To minimize space utilization, a portion of the hardware scb stores
 * different data during different portions of a SCSI transaction.
 * As initialized by the host driver for the initiator role, this area
 * contains the SCSI cdb (or a pointer to the  cdb) to be executed.  After
 * the cdb has been presented to the target, this area serves to store
 * residual transfer information and the SCSI status byte.
 * For the target role, the contents of this area do not change, but
 * still serve a different purpose than for the initiator role.  See
 * struct target_data for details.
 */

/*
 * Status information embedded in the shared poriton of
 * an SCB after passing the cdb to the target.  The kernel
 * driver will only read this data for transactions that
 * complete abnormally.
 */
struct initiator_status {
	uint32_t residual_datacnt;	/* Residual in the current S/G seg */
	uint32_t residual_sgptr;	/* The next S/G for this transfer */
	uint8_t	 scsi_status;		/* Standard SCSI status byte */
};

struct target_status {
	uint32_t residual_datacnt;	/* Residual in the current S/G seg */
	uint32_t residual_sgptr;	/* The next S/G for this transfer */
	uint8_t  scsi_status;		/* SCSI status to give to initiator */
	uint8_t  target_phases;		/* Bitmap of phases to execute */
	uint8_t  data_phase;		/* Data-In or Data-Out */
	uint8_t  initiator_tag;		/* Initiator's transaction tag */
};

/*
 * Initiator mode SCB shared data area.
 * If the embedded CDB is 12 bytes or less, we embed
 * the sense buffer address in the SCB.  This allows
 * us to retrieve sense information without interupting
 * the host in packetized mode.
 */
typedef uint32_t sense_addr_t;
#define MAX_CDB_LEN 16
#define MAX_CDB_LEN_WITH_SENSE_ADDR (MAX_CDB_LEN - sizeof(sense_addr_t))
union initiator_data {
	uint64_t cdbptr;
	uint8_t	 cdb[MAX_CDB_LEN];
	struct {
		uint8_t	 cdb[MAX_CDB_LEN_WITH_SENSE_ADDR];
		sense_addr_t sense_addr;
	} cdb_plus_saddr;
};

/*
 * Target mode version of the shared data SCB segment.
 */
struct target_data {
	uint32_t spare[2];	
	uint8_t  scsi_status;		/* SCSI status to give to initiator */
	uint8_t  target_phases;		/* Bitmap of phases to execute */
	uint8_t  data_phase;		/* Data-In or Data-Out */
	uint8_t  initiator_tag;		/* Initiator's transaction tag */
};

struct hardware_scb {
/*0*/	union {
		union	initiator_data idata;
		struct	target_data tdata;
		struct	initiator_status istatus;
		struct	target_status tstatus;
	} shared_data;
/*
 * A word about residuals.
 * The scb is presented to the sequencer with the dataptr and datacnt
 * fields initialized to the contents of the first S/G element to
 * transfer.  The sgptr field is initialized to the bus address for
 * the S/G element that follows the first in the in core S/G array
 * or'ed with the SG_FULL_RESID flag.  Sgptr may point to an invalid
 * S/G entry for this transfer (single S/G element transfer with the
 * first elements address and length preloaded in the dataptr/datacnt
 * fields).  If no transfer is to occur, sgptr is set to SG_LIST_NULL.
 * The SG_FULL_RESID flag ensures that the residual will be correctly
 * noted even if no data transfers occur.  Once the data phase is entered,
 * the residual sgptr and datacnt are loaded from the sgptr and the
 * datacnt fields.  After each S/G element's dataptr and length are
 * loaded into the hardware, the residual sgptr is advanced.  After
 * each S/G element is expired, its datacnt field is checked to see
 * if the LAST_SEG flag is set.  If so, SG_LIST_NULL is set in the
 * residual sg ptr and the transfer is considered complete.  If the
 * sequencer determines that there is a residual in the tranfer, or
 * there is non-zero status, it will set the SG_STATUS_VALID flag in
 * sgptr and dma the scb back into host memory.  To sumarize:
 *
 * Sequencer:
 *	o A residual has occurred if SG_FULL_RESID is set in sgptr,
 *	  or residual_sgptr does not have SG_LIST_NULL set.
 *
 *	o We are transfering the last segment if residual_datacnt has
 *	  the SG_LAST_SEG flag set.
 *
 * Host:
 *	o A residual can only have occurred if a completed scb has the
 *	  SG_STATUS_VALID flag set.  Inspection of the SCSI status field,
 *	  the residual_datacnt, and the residual_sgptr field will tell
 *	  for sure.
 *
 *	o residual_sgptr and sgptr refer to the "next" sg entry
 *	  and so may point beyond the last valid sg entry for the
 *	  transfer.
 */ 
#define SG_PTR_MASK	0xFFFFFFF8
/*16*/	uint8_t  cdb_len;
/*17*/	uint8_t  task_management;
/*18*/	uint16_t tag;
/*20*/	uint32_t next_hscb_busaddr;
/*24*/	uint64_t dataptr;
/*32*/	uint32_t datacnt;	/* Byte 3 is spare. */
/*36*/	uint32_t sgptr;
/*40*/	uint8_t  control;	/* See SCB_CONTROL in aic79xx.reg for details */
/*41*/	uint8_t	 scsiid;	/*
				 * Selection out Id
				 * Our Id (bits 0-3) Their ID (bits 4-7)
				 */
/*42*/	uint8_t  lun;
/*43*/	uint8_t  task_attribute_nonpkt_tag;
/*44*/	uint32_t hscb_busaddr;
/******* Fields below are not Downloaded (Sequencer may use for scratch) ******/
/*48*/  uint8_t	 spare[16];
};

/************************ Kernel SCB Definitions ******************************/
/*
 * Some fields of the SCB are OS dependent.  Here we collect the
 * definitions for elements that all OS platforms need to include
 * in there SCB definition.
 */

/*