📄 ispvar.h
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/* @(#)ispvar.h 1.37 *//* * Soft Definitions for for Qlogic ISP SCSI adapters. * * Copyright (c) 1997, 1998, 1999, 2000 by Matthew Jacob * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice immediately at the beginning of the file, without modification, * this list of conditions, and the following disclaimer. * 2. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */#ifndef _ISPVAR_H#define _ISPVAR_H#if defined(__NetBSD__) || defined(__OpenBSD__)#include <dev/ic/ispmbox.h>#ifdef ISP_TARGET_MODE#include <dev/ic/isp_target.h>#include <dev/ic/isp_tpublic.h>#endif#endif#ifdef __FreeBSD__#include <dev/isp/ispmbox.h>#ifdef ISP_TARGET_MODE#include <dev/isp/isp_target.h>#include <dev/isp/isp_tpublic.h>#endif#endif#ifdef __linux__#include "ispmbox.h"#ifdef ISP_TARGET_MODE#include "isp_target.h"#include "isp_tpublic.h"#endif#endif#define ISP_CORE_VERSION_MAJOR 2#define ISP_CORE_VERSION_MINOR 6/* * Vector for bus specific code to provide specific services. */struct ispsoftc;struct ispmdvec { int (*dv_rd_isr) (struct ispsoftc *, u_int16_t *, u_int16_t *, u_int16_t *); u_int16_t (*dv_rd_reg) (struct ispsoftc *, int); void (*dv_wr_reg) (struct ispsoftc *, int, u_int16_t); int (*dv_mbxdma) (struct ispsoftc *); int (*dv_dmaset) (struct ispsoftc *, XS_T *, ispreq_t *, u_int16_t *, u_int16_t); void (*dv_dmaclr) (struct ispsoftc *, XS_T *, u_int16_t); void (*dv_reset0) (struct ispsoftc *); void (*dv_reset1) (struct ispsoftc *); void (*dv_dregs) (struct ispsoftc *, const char *); u_int16_t *dv_ispfw; /* ptr to f/w */ u_int16_t dv_conf1; u_int16_t dv_clock; /* clock frequency */};/* * Overall parameters */#define MAX_TARGETS 16#define MAX_FC_TARG 256#define ISP_MAX_TARGETS(isp) (IS_FC(isp)? MAX_FC_TARG : MAX_TARGETS)#define ISP_MAX_LUNS(isp) (isp)->isp_maxluns/* * 'Types' */#ifndef ISP_DMA_ADDR_T#define ISP_DMA_ADDR_T u_int32_t#endif/* * Macros to access ISP registers through bus specific layers- * mostly wrappers to vector through the mdvec structure. */#define ISP_READ_ISR(isp, isrp, semap, mbox0p) \ (*(isp)->isp_mdvec->dv_rd_isr)(isp, isrp, semap, mbox0p)#define ISP_READ(isp, reg) \ (*(isp)->isp_mdvec->dv_rd_reg)((isp), (reg))#define ISP_WRITE(isp, reg, val) \ (*(isp)->isp_mdvec->dv_wr_reg)((isp), (reg), (val))#define ISP_MBOXDMASETUP(isp) \ (*(isp)->isp_mdvec->dv_mbxdma)((isp))#define ISP_DMASETUP(isp, xs, req, iptrp, optr) \ (*(isp)->isp_mdvec->dv_dmaset)((isp), (xs), (req), (iptrp), (optr))#define ISP_DMAFREE(isp, xs, hndl) \ if ((isp)->isp_mdvec->dv_dmaclr) \ (*(isp)->isp_mdvec->dv_dmaclr)((isp), (xs), (hndl))#define ISP_RESET0(isp) \ if ((isp)->isp_mdvec->dv_reset0) (*(isp)->isp_mdvec->dv_reset0)((isp))#define ISP_RESET1(isp) \ if ((isp)->isp_mdvec->dv_reset1) (*(isp)->isp_mdvec->dv_reset1)((isp))#define ISP_DUMPREGS(isp, m) \ if ((isp)->isp_mdvec->dv_dregs) (*(isp)->isp_mdvec->dv_dregs)((isp),(m))#define ISP_SETBITS(isp, reg, val) \ (*(isp)->isp_mdvec->dv_wr_reg)((isp), (reg), ISP_READ((isp), (reg)) | (val))#define ISP_CLRBITS(isp, reg, val) \ (*(isp)->isp_mdvec->dv_wr_reg)((isp), (reg), ISP_READ((isp), (reg)) & ~(val))/* * The MEMORYBARRIER macro is defined per platform (to provide synchronization * on Request and Response Queues, Scratch DMA areas, and Registers) * * Defined Memory Barrier Synchronization Types */#define SYNC_REQUEST 0 /* request queue synchronization */#define SYNC_RESULT 1 /* result queue synchronization */#define SYNC_SFORDEV 2 /* scratch, sync for ISP */#define SYNC_SFORCPU 3 /* scratch, sync for CPU */#define SYNC_REG 4 /* for registers *//* * Request/Response Queue defines and macros. * The maximum is defined per platform (and can be based on board type). *//* This is the size of a queue entry (request and response) */#define QENTRY_LEN 64/* Both request and result queue length must be a power of two */#define RQUEST_QUEUE_LEN(x) MAXISPREQUEST(x)#ifdef ISP_TARGET_MODE#define RESULT_QUEUE_LEN(x) MAXISPREQUEST(x)#else#define RESULT_QUEUE_LEN(x) \ (((MAXISPREQUEST(x) >> 2) < 64)? 64 : MAXISPREQUEST(x) >> 2)#endif#define ISP_QUEUE_ENTRY(q, idx) ((q) + ((idx) * QENTRY_LEN))#define ISP_QUEUE_SIZE(n) ((n) * QENTRY_LEN)#define ISP_NXT_QENTRY(idx, qlen) (((idx) + 1) & ((qlen)-1))#define ISP_QFREE(in, out, qlen) \ ((in == out)? (qlen - 1) : ((in > out)? \ ((qlen - 1) - (in - out)) : (out - in - 1)))#define ISP_QAVAIL(isp) \ ISP_QFREE(isp->isp_reqidx, isp->isp_reqodx, RQUEST_QUEUE_LEN(isp))#define ISP_ADD_REQUEST(isp, nxti) \ MEMORYBARRIER(isp, SYNC_REQUEST, isp->isp_reqidx, QENTRY_LEN); \ WRITE_REQUEST_QUEUE_IN_POINTER(isp, nxti); \ isp->isp_reqidx = nxti/* * SCSI Specific Host Adapter Parameters- per bus, per target */typedef struct { u_int isp_gotdparms : 1, isp_req_ack_active_neg : 1, isp_data_line_active_neg: 1, isp_cmd_dma_burst_enable: 1, isp_data_dma_burst_enabl: 1, isp_fifo_threshold : 3, isp_ultramode : 1, isp_diffmode : 1, isp_lvdmode : 1, isp_fast_mttr : 1, /* fast sram */ isp_initiator_id : 4, isp_async_data_setup : 4; u_int16_t isp_selection_timeout; u_int16_t isp_max_queue_depth; u_int8_t isp_tag_aging; u_int8_t isp_bus_reset_delay; u_int8_t isp_retry_count; u_int8_t isp_retry_delay; struct { u_int32_t exc_throttle : 8, : 1, dev_enable : 1, /* ignored */ dev_update : 1, dev_refresh : 1, actv_offset : 4, goal_offset : 4, nvrm_offset : 4; u_int8_t actv_period; /* current sync period */ u_int8_t goal_period; /* goal sync period */ u_int8_t nvrm_period; /* nvram sync period */ u_int16_t actv_flags; /* current device flags */ u_int16_t goal_flags; /* goal device flags */ u_int16_t nvrm_flags; /* nvram device flags */ } isp_devparam[MAX_TARGETS];} sdparam;/* * Device Flags */#define DPARM_DISC 0x8000#define DPARM_PARITY 0x4000#define DPARM_WIDE 0x2000#define DPARM_SYNC 0x1000#define DPARM_TQING 0x0800#define DPARM_ARQ 0x0400#define DPARM_QFRZ 0x0200#define DPARM_RENEG 0x0100#define DPARM_NARROW 0x0080#define DPARM_ASYNC 0x0040#define DPARM_PPR 0x0020#define DPARM_DEFAULT (0xFF00 & ~DPARM_QFRZ)#define DPARM_SAFE_DFLT (DPARM_DEFAULT & ~(DPARM_WIDE|DPARM_SYNC|DPARM_TQING))/* technically, not really correct, as they need to be rated based upon clock */#define ISP_80M_SYNCPARMS 0x0c09#define ISP_40M_SYNCPARMS 0x0c0a#define ISP_20M_SYNCPARMS 0x0c0c#define ISP_20M_SYNCPARMS_1040 0x080c#define ISP_10M_SYNCPARMS 0x0c19#define ISP_08M_SYNCPARMS 0x0c25#define ISP_05M_SYNCPARMS 0x0c32#define ISP_04M_SYNCPARMS 0x0c41/* * Fibre Channel Specifics */#define FL_PORT_ID 0x7e /* FL_Port Special ID */#define FC_PORT_ID 0x7f /* Fabric Controller Special ID */#define FC_SNS_ID 0x80 /* SNS Server Special ID *//* #define ISP_USE_GA_NXT 1 */ /* Use GA_NXT with switches */#ifndef GA_NXT_MAX#define GA_NXT_MAX 256#endiftypedef struct { u_int32_t isp_fwoptions : 16, isp_gbspeed : 2, isp_iid_set : 1, loop_seen_once : 1, isp_loopstate : 4, /* Current Loop State */ isp_fwstate : 3, /* ISP F/W state */ isp_gotdparms : 1, isp_topo : 3, isp_onfabric : 1; u_int8_t isp_iid; /* 'initiator' id */ u_int8_t isp_loopid; /* hard loop id */ u_int8_t isp_alpa; /* ALPA */ u_int32_t isp_portid; volatile u_int16_t isp_lipseq; /* LIP sequence # */ u_int16_t isp_fwattr; /* firmware attributes */ u_int8_t isp_execthrottle; u_int8_t isp_retry_delay; u_int8_t isp_retry_count; u_int8_t isp_reserved; u_int16_t isp_maxalloc; u_int16_t isp_maxfrmlen; u_int64_t isp_nodewwn; u_int64_t isp_portwwn; /* * Port Data Base. This is indexed by 'target', which is invariate. * However, elements within can move around due to loop changes, * so the actual loop ID passed to the F/W is in this structure. * The first time the loop is seen up, loopid will match the index * (except for fabric nodes which are above mapped above FC_SNS_ID * and are completely virtual), but subsequent LIPs can cause things * to move around. */ struct lportdb { u_int32_t port_type : 8, : 4, fc4_type : 4, loopid : 8, last_fabric_dev : 1, force_logout : 1, was_fabric_dev : 1,
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