qla2x00.h

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/********************************************************************************
*                  QLOGIC LINUX SOFTWARE
*
* QLogic ISP2x00 device driver for Linux 2.4.x
* Copyright (C) 2002 Qlogic Corporation
* (www.qlogic.com)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2, or (at your option) any
* later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
* General Public License for more details.
**
******************************************************************************/

#if !defined(_IO_HBA_QLA2100_H)		/* wrapper symbol for kernel use */
#define _IO_HBA_QLA2100_H		/* subject to change without notice */

#if !defined(LINUX_VERSION_CODE)
#include <linux/version.h>
#endif  /* LINUX_VERSION_CODE not defined */

#if !defined(HOSTS_C)

#if defined(__cplusplus)
extern "C" {
#endif

/*
 * Driver debug definitions.
 */
/* #define QL_DEBUG_LEVEL_1  */ /* Output register accesses to COM1 */
/* #define QL_DEBUG_LEVEL_2  */ /* Output error msgs to COM1 */
/* #define QL_DEBUG_LEVEL_3  */ /* Output function trace msgs to COM1 */
/* #define QL_DEBUG_LEVEL_4  */ /* Output NVRAM trace msgs to COM1 */
/* #define QL_DEBUG_LEVEL_5  */ /* Output ring trace msgs to COM1 */
/* #define QL_DEBUG_LEVEL_6  */ /* Output WATCHDOG timer trace to COM1 */
/* #define QL_DEBUG_LEVEL_7  */ /* Output RISC load trace msgs to COM1 */
/* #define QL_DEBUG_LEVEL_8  */ /* Output ring saturation msgs to COM1 */
/* #define QL_DEBUG_LEVEL_9  */ /* Output IOCTL trace msgs */
/* #define QL_DEBUG_LEVEL_10 */ /* Output IOCTL error msgs */
/* #define QL_DEBUG_LEVEL_11 */ /* Output Mbx Cmd trace msgs */
/* #define QL_DEBUG_LEVEL_12 */ /* Output IP trace msgs */

#define QL_DEBUG_CONSOLE            /* Output to console */

#include <asm/bitops.h>
#include <asm/semaphore.h>

/*
 * Data bit definitions.
 */
#define BIT_0   0x1
#define BIT_1   0x2
#define BIT_2   0x4
#define BIT_3   0x8
#define BIT_4   0x10
#define BIT_5   0x20
#define BIT_6   0x40
#define BIT_7   0x80
#define BIT_8   0x100
#define BIT_9   0x200
#define BIT_10  0x400
#define BIT_11  0x800
#define BIT_12  0x1000
#define BIT_13  0x2000
#define BIT_14  0x4000
#define BIT_15  0x8000
#define BIT_16  0x10000
#define BIT_17  0x20000
#define BIT_18  0x40000
#define BIT_19  0x80000
#define BIT_20  0x100000
#define BIT_21  0x200000
#define BIT_22  0x400000
#define BIT_23  0x800000
#define BIT_24  0x1000000
#define BIT_25  0x2000000
#define BIT_26  0x4000000
#define BIT_27  0x8000000
#define BIT_28  0x10000000
#define BIT_29  0x20000000
#define BIT_30  0x40000000
#define BIT_31  0x80000000

#define LS_64BITS(x)    (uint32_t)(0xffffffff & ((u64)x))
#define MS_64BITS(x)    (uint32_t)(0xffffffff & (((u64)x)>>16>>16) )

#define MSB(x)          (uint8_t)(((uint16_t)(x) >> 8) & 0xff)
#define LSB(x)          (uint8_t)(x & 0xff)
#define MSW(x)          (uint16_t)(((uint32_t)(x) >> 16) & 0xffff)
#define LSW(x)          (uint16_t)(x & 0xffff)
#define QL21_64BITS_3RDWD(x)   ((uint16_t) (( (x) >> 16) >> 16) & 0xffff)
#define QL21_64BITS_4THWD(x)   ((uint16_t) ((( (x) >>16)>>16)>>16) & 0xffff)

/*
 *  Local Macro Definitions.
 */
#if defined(QL_DEBUG_LEVEL_1) || defined(QL_DEBUG_LEVEL_2) || \
    defined(QL_DEBUG_LEVEL_3) || defined(QL_DEBUG_LEVEL_4) || \
    defined(QL_DEBUG_LEVEL_5) || defined(QL_DEBUG_LEVEL_6) || \
    defined(QL_DEBUG_LEVEL_7) || defined(QL_DEBUG_LEVEL_8) || \
    defined(QL_DEBUG_LEVEL_9) || defined(QL_DEBUG_LEVEL_10) || \
    defined(QL_DEBUG_LEVEL_11)
    #define QL_DEBUG_ROUTINES
#endif

#if !defined(TRUE)
    #define TRUE  1
#endif

#if !defined(FALSE)
    #define FALSE 0
#endif

typedef char BOOL;


/* 
 * Locking
 */
#include <linux/smp.h>
#define cpuid smp_processor_id()

/*
 * I/O register
*/
/* #define MEMORY_MAPPED_IO  */    /* Enable memory mapped I/O */
#undef MEMORY_MAPPED_IO            /* Disable memory mapped I/O */

#if defined(MEMORY_MAPPED_IO)
#define RD_REG_BYTE(addr)         readb(addr)
#define RD_REG_WORD(addr)         readw(addr)
#define RD_REG_DWORD(addr)        readl(addr)
#define WRT_REG_BYTE(addr, data)  writeb(data,addr)
#define WRT_REG_WORD(addr, data)  writew(data,addr)
#define WRT_REG_DWORD(addr, data) writel(data,addr)
#else   /* MEMORY_MAPPED_IO */
#define RD_REG_BYTE(addr)         (inb((unsigned long)addr))
#define RD_REG_WORD(addr)         (inw((unsigned long)addr))
#define RD_REG_DWORD(addr)        (inl((unsigned long)addr))
#define WRT_REG_BYTE(addr, data)  (outb(data,(unsigned long)addr))
#define WRT_REG_WORD(addr, data)  (outw(data,(unsigned long)addr))
#define WRT_REG_DWORD(addr, data) (outl(data,(unsigned long)addr))
#endif  /* MEMORY_MAPPED_IO */
/*
 * Fibre Channel device definitions.
 */
#define WWN_SIZE		8	/* Size of WWPN, WWN & WWNN */
#define MAX_FIBRE_DEVICES   	256
#define MAX_FIBRE_LUNS  	256
#define	MAX_RSCN_COUNT		10
#define	MAX_HOST_COUNT		16

/*
 * Host adapter default definitions.
 */
#define MAX_BUSES            1  /* We only have one bus today */
#define MAX_TARGETS_2100     MAX_FIBRE_DEVICES
#define MAX_TARGETS_2200     MAX_FIBRE_DEVICES
#define MAX_TARGETS          MAX_FIBRE_DEVICES
#define MAX_LUNS             MAX_FIBRE_LUNS
#define MAX_CMDS_PER_LUN     255 
#define MAX_SRBS             4096


                                    
/*
 * Fibre Channel device definitions.
 */
#define LAST_LOCAL_LOOP_ID  0x7d
#define SNS_FL_PORT         0x7e
#define FABRIC_CONTROLLER   0x7f
#define SIMPLE_NAME_SERVER  0x80
#define SNS_FIRST_LOOP_ID   0x81
#define LAST_SNS_LOOP_ID    0xfe
#define MANAGEMENT_SERVER   0xfe
#define BROADCAST           0xff
#define SNS_ACCEPT          0x0280      /* 8002 swapped */
#define SNS_REJECT          0x0180      /* 8001 swapped */

/* Loop ID's used as database flags, must be higher than any valid Loop ID */
#define PORT_UNUSED         0x100       /* Port never been used. */
#define PORT_AVAILABLE      0x101       /* Device does not exist on port. */
#define PORT_NEED_MAP       0x102       
#define PORT_LOST_ID        0x200       
#define PORT_LOGIN_NEEDED   0x400       

/*
 * Timeout timer counts in seconds
 */
#define QLA2100_WDG_TIME_QUANTUM   5    /* In seconds */
#define PORT_RETRY_TIME            2
#define LOOP_DOWN_TIMEOUT          60
#define LOOP_DOWN_TIME             60 		/* 240 */
#define	LOOP_DOWN_RESET		(LOOP_DOWN_TIME - 30)

/* Maximum outstanding commands in ISP queues (1-65535) */
#define MAX_OUTSTANDING_COMMANDS   1024

/* ISP request and response entry counts (37-65535) */
#define REQUEST_ENTRY_CNT       128     /* Number of request entries. */
#if defined(ISP2100) || defined(ISP2200)
#define RESPONSE_ENTRY_CNT      64      /* Number of response entries.*/
#else
#define RESPONSE_ENTRY_CNT      512     /* Number of response entries.*/
#endif

#define  SCSI_BUS_32(scp)   ((scp)->channel)
#define  SCSI_TCN_32(scp)    ((scp)->target)
#define  SCSI_LUN_32(scp)    ((scp)->lun)



/*
 * UnixWare required definitions.
 */
#define HBA_PREFIX qla2100

/* Physical DMA memory requirements */
#define QLA2100_MEMALIGN    4
#define QLA2100_BOUNDARY    0x80000000  /* 2GB */

/* Number of segments 1 - 65535 */
#define SG_SEGMENTS     32             /* Cmd entry + 6 continuations */

/*
 * SCSI Request Block 
 */
typedef struct srb
{
    struct list_head   list;
    struct srb  *s_next;             /* (4) Next block on LU queue */
    struct srb  *s_prev;             /* (4) Previous block on LU queue */
    Scsi_Cmnd  *cmd;                 /* Linux SCSI command pkt */
    struct scsi_qla_host *ha;		/* ha this SP is queued on */
    uint8_t     more_cdb[4];         /* For 16 bytes CDB pass thru cmd since
                                        linux SCSI cdb is 12 bytes. */ 
    uint8_t     dir;                 /* direction of transfer */
    uint8_t     unused1;
    uint8_t     ccode;               /* risc completion code */
    uint8_t     scode;               /* scsi status code */
    
    uint16_t    flags;               /* Status flags - defined below */
    uint16_t     state;
#define SRB_FREE_STATE          0    /* Request returned back */
#define SRB_PENDING_STATE       1    /* Request being queued in LUN Q */
#define SRB_ACTIVE_STATE        2    /* Request in Active Array */
#define SRB_DONE_STATE          3    /* Request Queued in Done Queue */
#define SRB_RETRY_STATE         4    /* Request in Retry Queue */
#define SRB_SUSPENDED_STATE     5    /* Request in suspended state */
#define SRB_NO_QUEUE_STATE      6    /* Request is in between states */
#define SRB_ACTIVE_TIMEOUT_STATE 7   /* Request in Active Array but timed out */
#define SRB_FAILOVER_STATE 	8    /* Request in Failover Queue */
#define SRB_SCSI_RETRY_STATE    9    /* Request in Scsi Retry Queue */

    uint8_t     used;		     /* used by allocation code */
    uint8_t     ref_num;             /* reference SRB number */	
    uint16_t    magic;               /* qlogic magic number */
#define SRB_MAGIC       0x10CB

    u_long      host_no;             /* Host number of allocating host */
    struct      timer_list   timer;  /* used to timeout command */
    dma_addr_t	 saved_dma_handle;    /* for unmap of single transfers */

    atomic_t	 ref_count;	      /* reference count for this structure */			
	/* Target/LUN queue pointers. */
    struct os_tgt		*tgt_queue;	/* ptr to visible ha's target */
    struct os_lun		*lun_queue;	/* ptr to visible ha's lun */
	struct fc_lun		*fclun;		/* FC LUN context pointer. */
	/* Raw completion info for use by failover ? */
    uint8_t	fo_retry_cnt;	/* Retry count this request */
    uint8_t	err_id;		/* error id */
    uint8_t	cmd_length;		/* command length */
    uint8_t	unused3;

    int      delay;             /* delay in seconds */
    int      ext_history;             /*  */
	
    u_long      e_start;             /* jiffies at start of extend timeout */
    u_long      r_start;             /* jiffies at start of request */
    u_long      u_start;             /* jiffies when sent to F/W    */
    u_long      f_start;            /*ra 10/29/01*/ /*jiffies when put in failov					er queue*/
    uint32_t    resid;              /* Residual transfer length */
    uint16_t    sense_len;          /* Sense data length */

    uint32_t 	 iocb_cnt;
}srb_t;

/*
 * SRB flag definitions
 */
#define SRB_TIMEOUT          BIT_0	/* Command timed out */
#define SRB_DMA_VALID        BIT_1	/* Command sent to ISP */
#define SRB_WATCHDOG         BIT_2	/* Command on watchdog list */
#define SRB_ABORT_PENDING    BIT_3	/* Command abort sent to device */

#define SRB_ABORTED          BIT_4	/* Command aborted command already */
#define SRB_RETRY            BIT_5	/* Command needs retrying */
#define SRB_GOT_SENSE	     BIT_6	/* Command has sense data */
#define SRB_FAILOVER         BIT_7	/* Command in failover state */

#define SRB_BUSY             BIT_8	/* Command is in busy retry state */
#define SRB_FO_CANCEL        BIT_9	/* Command don't need to do failover */
#define	SRB_IOCTL	     BIT_10	/* IOCTL command. */
#define	SRB_ISP_STARTED	     BIT_11	/* Command sent to ISP. */

#define	SRB_ISP_COMPLETED    BIT_12	/* ISP finished with command */


/*
 *  ISP PCI Configuration Register Set
 */
typedef volatile struct
{
    uint16_t vendor_id;                 /* 0x0 */
    uint16_t device_id;                 /* 0x2 */
    uint16_t command;                   /* 0x4 */
    uint16_t status;                    /* 0x6 */
    uint8_t revision_id;                /* 0x8 */
    uint8_t programming_interface;      /* 0x9 */
    uint8_t sub_class;                  /* 0xa */
    uint8_t base_class;                 /* 0xb */
    uint8_t cache_line;                 /* 0xc */
    uint8_t latency_timer;              /* 0xd */
    uint8_t header_type;                /* 0xe */
    uint8_t bist;                       /* 0xf */
    uint32_t base_port;                 /* 0x10 */
    uint32_t mem_base_addr;             /* 0x14 */
    uint32_t base_addr[4];              /* 0x18-0x24 */
    uint32_t reserved_1[2];             /* 0x28-0x2c */
    uint16_t expansion_rom;             /* 0x30 */
    uint32_t reserved_2[2];             /* 0x34-0x38 */
    uint8_t interrupt_line;             /* 0x3c */
    uint8_t interrupt_pin;              /* 0x3d */
    uint8_t min_grant;                  /* 0x3e */
    uint8_t max_latency;                /* 0x3f */
}config_reg_t __attribute__((packed));


#if defined(ISP2100) || defined(ISP2200)
/*
 *  ISP I/O Register Set structure definitions for ISP2200 and ISP2100.
 */
typedef volatile struct
{
    uint16_t flash_address;             /* Flash BIOS address */
    uint16_t flash_data;                /* Flash BIOS data */
    uint16_t unused_1[1];               /* Gap */
    uint16_t ctrl_status;               /* Control/Status */