lh7a404_sci.h

在sharp 404开发板的串口测试代码

#define SCI_RXFF                    0x00000004
/* SCI FIFO status register receive FIFO empty bit */
#define SCI_RXFE                    0x00000008

/***********************************************************************
 * SCI Read timeout register defines
 **********************************************************************/ 

/* SCI Read Timeout register load macro */
#define SCI_RXTIME(n)               _SBF(0, (n & 0xFFFF))

/***********************************************************************
 * SCI status register defines
 **********************************************************************/ 

/* SCI status register power enabled bit */
#define SCI_POWER                   0x00000001
/* SCI status register reset bit */
#define SCI_CRESET                  0x00000002
/* SCI status register smart clock enabled bit */
#define SCI_CLKEN                   0x00000004
/* SCI status register data enabled bit */
#define SCI_DATAEN                  0x00000008
/* SCI status register clock output enabled bit */
#define SCI_CLKOUTEN                0x00000010
/* SCI status register clock enabled bit */
#define SCI_CLKENB                  0x00000020
/* SCI status register CLKOUT bit */
#define SCI_CLKOUT                  0x00000040
/* SCI status register data output enable bit */
#define SCI_DATAOUTEN               0x00000080
/* SCI status register data enabled bit */
#define SCI_DATAENB                 0x00000100
/* SCI status register card present bit */
#define SCI_CARDPRESENT             0x00000200

/***********************************************************************
 * SCI Debounce Timer register defines
 **********************************************************************/ 

/* SCI Debounce Timer register load macro */
#define SCI_STABLE(n)               _SBF(0, (n & 0xFF))

/***********************************************************************
 * SCI Activation Time Event register defines
 **********************************************************************/ 

/* SCI Activation Time Event register load macro */
#define SCI_ATIME(n)                _SBF(0, (n & 0xFFFF))

/***********************************************************************
 * SCI Deactivation Time Event register defines
 **********************************************************************/ 

/* SCI Deactivation Time Event register load macro */
#define SCI_DTIME(n)                _SBF(0, (n & 0xFFFF))

/***********************************************************************
 * SCI Time to ATR reception register defines
 **********************************************************************/ 

/* SCI Time to ATR reception register load macro */
#define SCI_ATRSTIME(n)             _SBF(0, (n & 0xFFFF))

/***********************************************************************
 * SCI ATR Duration Timeout register defines
 **********************************************************************/ 

/* SCI ATR Duration Timeout register load macro */
#define SCI_ATRDTIME(n)             _SBF(0, (n & 0xFFFF))

/***********************************************************************
 * SCI Block to Block Timeout defines
 **********************************************************************/ 

/* SCI Block to Block Timeout register load macro */
#define SCI_BLKTIME(n)              _SBF(0, (n & 0xFFFF))

/***********************************************************************
 * SCI Char to Char Timeout register defines
 **********************************************************************/ 

/* SCI Char to Char Timeout register load macro */
#define SCI_CHTIME(n)               _SBF(0, (n & 0xFFFF))

/***********************************************************************
 * SCI Char Clock Divider register defines
 **********************************************************************/ 

/* SCI Char Clock Divider register load macro */
#define SCI_CLKDIV(n)               _SBF(0, (n & 0xFFFF))

/***********************************************************************
 * SCI Baud Rate Clock register defines
 **********************************************************************/ 

/* SCI Baud Rate Clock register load macro */
#define SCI_BAUD(n)                 _SBF(0, (n & 0xFFFF))

/***********************************************************************
 * SCI Baud Cycle register defines
 **********************************************************************/ 

/* SCI Baud Cycle register load macro */
#define SCI_BAUD_CYC(n)             _SBF(0, (n & 0xFFFF))

/***********************************************************************
 * SCI Char to Char Guard Time register defines
 **********************************************************************/ 

/* SCI Char to Char Guard Time register load macro */
#define SCI_CHGUARD(n)              _SBF(0, (n & 0xFF))

/***********************************************************************
 * SCI Block to Block Guard Time register defines
 **********************************************************************/ 

/* SCI Block to Block Guard Time register load macro */
#define SCI_BLKGUARD(n)             _SBF(0, (n & 0xFF))

/***********************************************************************
 * SCI Sync / Async Select register defines
 **********************************************************************/ 

/* SCI Sync / Async Select register sync data bit */
#define SCI_SELDATA                 0x00000001
/* SCI Sync / Async Select register sync clock bit */
#define SCI_SELCLK                  0x00000002

/***********************************************************************
 * SCI Sync Data Select register defines
 **********************************************************************/ 

/* SCI Sync Data Select register write data select bit */
#define SCI_WDATA                   0x00000001
/* SCI Sync Data Select register write clock select bit */
#define SCI_WCLK                    0x00000002
/* SCI Sync Data Select register write data enable select bit */
#define SCI_WDATAEN                 0x00000004
/* SCI Sync Data Select register write clock enable select bit */
#define SCI_WCLKEN                  0x00000008

/***********************************************************************
 * SCI Raw Clock Status register defines
 **********************************************************************/ 

/* SCI Raw Clock Status register SCIO signal value bit */
#define SCI_RDATA                   0x00000001
/* SCI Raw Clock Status register SCCLK signal value bit */
#define SCI_RCLK                    0x00000002

/***********************************************************************
 * SCI Interrupt Status register defines
 **********************************************************************/ 

/* SCI Interrupt Status registers card inserted bit */
#define SCI_CARDININTR              0x00000001
/* SCI Interrupt Status registers card taken out bit */
#define SCI_CARDOUTINTR             0x00000002
/* SCI Interrupt Status registers card activated bit */
#define SCI_CARDUPINTR              0x00000004
/* SCI Interrupt Status registers card de-activated bit */
#define SCI_CARDDNINTR              0x00000008
/* SCI Interrupt Status registers transmit error bit */
#define SCI_TXERRINTR               0x00000010
/* SCI Interrupt Status registers answer to reset start timeout bit */
#define SCI_ATRSTOUTINTR            0x00000020
/* SCI Interrupt Status registers answer to reset dur timeout bit */
#define SCI_ATRDTOUTINTR            0x00000040
/* SCI Interrupt Status registers block timeout timeout bit */
#define SCI_BLKTOUTINTR             0x00000080
/* SCI Interrupt Status registers character timeout timeout bit */
#define SCI_CHTOUTINTR              0x00000100
/* SCI Interrupt Status registers read timeout timeout bit */
#define SCI_RTOUTINTR               0x00000200
/* SCI Interrupt Status registers receive watermark bit */
#define SCI_RXWMARKINTR             0x00000400
/* SCI Interrupt Status registers transmit watermark bit */
#define SCI_TXWMARKINTR             0x00000800

/***********************************************************************
 * SCI Interrupt Status register defines
 **********************************************************************/ 

/* SCI Interrupt Status registers all interrupt bits */
#define SCI_ALLINTS                 0x00000FFF

/***********************************************************************
 * SCI Control register register defines
 **********************************************************************/ 

/* SCI Control register smart card interface enable bit */
#define SCI_EN                      0x00000001
/* SCI Control register pre-divisor is 2 enable bit */
#define SCI_PREDIV                  0x00000002
/* SCI Control register GPIO B5 pin is SCI VCC enable bit */
#define SCI_MUX_VCCEN               0x00000010
/* SCI Control register GPIO D6 pin is SCI DETECT enable bit */
#define SCI_MUX_DETECT              0x00000020

/* Macro pointing to WDT registers */
#define SCI ((SCI_REGS_T *)(SCI_BASE))

#endif /* LH7A404_SCI_H */