lh7a404_sci.h

在sharp 404开发板的串口测试代码

/***********************************************************************
 * $Workfile:   lh7a404_sci.h  $
 * $Revision:   1.1  $
 * $Author:   WellsK  $
 * $Date:   Jul 01 2003 10:59:40  $
 *
 * Project: LH7A404 SCI definitions
 *
 * Description:
 *     This file contains the structure definitions and manifest
 *     constants for the LH7A404 component:
 *         Smart Card Interface
 *
 * $Log:   //smaicnt2/pvcs/VM/sharpmcu/archives/sharpmcu/software/csps/lh7a404/include/lh7a404_sci.h-arc  $
 * 
 *    Rev 1.1   Jul 01 2003 10:59:40   WellsK
 * Changed to use abl_types instead of sma_types.
 * 
 *    Rev 1.0   Jun 30 2003 16:28:52   WellsK
 * Initial revision.
 * 
 * 
 ***********************************************************************
 * SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION
 * OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE,
 * AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES, 
 * SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE.
 *
 * SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY 
 * FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A 
 * SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT. USE OF THIS SOURCE
 * FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS.
 *
 * COPYRIGHT (C) 2001 SHARP MICROELECTRONICS OF THE AMERICAS, INC.
 *     CAMAS, WA
 **********************************************************************/

#ifndef LH7A404_SCI_H
#define LH7A404_SCI_H

#include "abl_types.h"
#include "lh7a404_chip.h"

/***********************************************************************
 * SCI Register Module Structure
 **********************************************************************/

/* SCI Module Register Structure */ 
typedef struct
{
    volatile UNS_32 data;          /* SCI Data register */
    volatile UNS_32 cr0;           /* SCI Control register zero */
    volatile UNS_32 cr1;           /* SCI Control register one */
    volatile UNS_32 cr2;           /* SCI Control register two */
    volatile UNS_32 ier;           /* SCI Interrupt Enable register */
    volatile UNS_32 retry;         /* SCI Retry Limit register */
    volatile UNS_32 wmark;         /* SCI FIFO Tide water mark reg */
    volatile UNS_32 txcount;       /* SCI TX FIFO Count Clear reg */
    volatile UNS_32 rxcount;       /* SCI TX FIFO Count Clear reg */
    volatile UNS_32 fr;            /* SCI FIFO status register */
    volatile UNS_32 rxtime;        /* SCI Receive Read timeout reg */
    volatile UNS_32 dstat;         /* SCI Direct Status register */
    volatile UNS_32 stable;        /* SCI De-Bounce timer register */
    volatile UNS_32 atime;         /* SCI Activation Event time reg */
    volatile UNS_32 dtime;         /* SCI Deactivation Event time reg */
    volatile UNS_32 atrstime;      /* SCI Time To Start ATR RX reg */
    volatile UNS_32 atrdtime;      /* SCI ATD Max char Duration reg */
    volatile UNS_32 blktime;       /* SCI Block to Block RX TimeOut */
    volatile UNS_32 chtime;        /* SCI Char to Char RX TimeOut */
    volatile UNS_32 clkdiv;        /* SCI External Clock Frequency */
    volatile UNS_32 baud;          /* SCI Baud rate clock register */
    volatile UNS_32 cycles;        /* SCI Baud Cycles register */
    volatile UNS_32 chguard;       /* SCI Char-Char extra guard time */
    volatile UNS_32 blkguard;      /* SCI Block Guard Time register */
    volatile UNS_32 synccr;        /* SCI Sync/Async mux control reg */
    volatile UNS_32 syncdata;      /* SCI Sync Data register */
    volatile UNS_32 rawstat;       /* SCI Raw I/O & clock status reg */
    volatile UNS_32 iir_icr;       /* SCI Interrupt ID/Clear register */
    volatile UNS_32 control;       /* SCI Enable/Pre-Divide register */
} SCI_REGS_T;

/***********************************************************************
 * SCI data register defines
 **********************************************************************/ 

/* SCI data register data load macro */
#define SCI_DATA(n)                 _SBF(0, (n & 0xFF))
/* SCI data register parity error bit */
#define SCI_PARITY                  0x00000100

/***********************************************************************
 * SCI control 0 register defines
 **********************************************************************/ 

/* SCI control register 0 data and parity sense bit */
#define SCI_SENSE                   0x00000001
/* SCI control register 0 data bit order inverse bit */
#define SCI_ORDER                   0x00000002
/* SCI control register 0 transmit parity odd bit */
#define SCI_TXPARITY                0x00000004
/* SCI control register 0 transmit T0 protocol bit */
#define SCI_TXNAK                   0x00000008
/* SCI control register 0 receive parity odd bit */
#define SCI_RXPARITY                0x00000010
/* SCI control register 0 receive T0 protocol bit */
#define SCI_RXNAK                   0x00000020

/***********************************************************************
 * SCI control 1 register defines
 **********************************************************************/ 

/* SCI control register 1 answer to reset duration timer start bit */
#define SCI_ATRDEN                  0x00000001
/* SCI control register 1 block timeout timer start bit */
#define SCI_BLKEN                   0x00000002
/* SCI control register 1 transmit mode bit */
#define SCI_MODE                    0x00000004
/* SCI control register 1 clock Z1 open-drain bit */
#define SCI_CLKZ1                   0x00000008
/* SCI control register 1 block guard timer start bit */
#define SCI_BGTEN                   0x00000010
/* SCI control register 1 enable debounce bypass bit */
#define SCI_EXDBNCE                 0x00000020

/***********************************************************************
 * SCI control 2 register defines
 **********************************************************************/ 

/* SCI control register 2 activate smart card session bit */
#define SCI_STARTUP                 0x00000001
/* SCI control register 2 es-activate smart card session bit */
#define SCI_FINISH                  0x00000002
/* SCI control register 2 warm reset bit */
#define SCI_WRESET                  0x00000004

/***********************************************************************
 * SCI interrupt enable register defines
 **********************************************************************/ 

/* SCI Interrupt Enable register card inserted bit */
#define SCI_CARDINIE                0x00000001
/* SCI Interrupt Enable register card taken-out bit */
#define SCI_CARDOUTIE               0x00000002
/* SCI Interrupt Enable register card power-up bit */
#define SCI_CARDUPIE                0x00000004
/* SCI Interrupt Enable register card power-down bit */
#define SCI_CARDDNIE                0x00000008
/* SCI Interrupt Enable register transmit error bit */
#define SCI_TXERRIE                 0x00000010
/* SCI Interrupt Enable register answer to reset start timeout bit */
#define SCI_ATRSTOUTIE              0x00000020
/* SCI Interrupt Enable register answer to reset duration timeout bit */
#define SCI_ATRDTOUTIE              0x00000040
/* SCI Interrupt Enable register block timeout bit */
#define SCI_BLKTOIE                 0x00000080
/* SCI Interrupt Enable register character timeout bit */
#define SCI_CHTOUTIE                0x00000100
/* SCI Interrupt Enable register receive timeout bit */
#define SCI_RTOUTIE                 0x00000200
/* SCI Interrupt Enable register receive watermark bit */
#define SCI_RXWMARKIE               0x00000400
/* SCI Interrupt Enable register transmit watermark bit */
#define SCI_TXWMARKIE               0x00000800

/***********************************************************************
 * SCI retry limit register defines
 **********************************************************************/ 

/* SCI Retry limit register transmit count load macro */
#define SCI_TXRETRY(n)              _SBF(0, (n & 0x7))
/* SCI Retry limit register receive count load macro */
#define SCI_RXRETRY(n)              _SBF(3, (n & 0x7))

/***********************************************************************
 * SCI FIFO watermark register defines
 **********************************************************************/ 

/* SCI FIFO Watermark register receive watermark load macro */
#define SCI_RXWMARK(n)              _SBF(0, (n & 0xF))
/* SCI FIFO Watermark register transmit watermark load macro */
#define SCI_TXWMARK(n)              _SBF(4, (n & 0xF))

/***********************************************************************
 * SCI TX FIFO count register defines
 **********************************************************************/ 

/* SCI TX FIFO Count register transmit FIFO count load macro */
#define SCI_TXCOUNT(n)              _SBF(0, (n & 0x1F))

/***********************************************************************
 * SCI RX FIFO count register defines
 **********************************************************************/ 

/* SCI RX FIFO Count register transmit FIFO count load macro */
#define SCI_RXCOUNT(n)              _SBF(0, (n & 0x1F))

/***********************************************************************
 * SCI FIFO status register defines
 **********************************************************************/ 

/* SCI FIFO status register transmit FIFO full bit */
#define SCI_TXFF                    0x00000001
/* SCI FIFO status register transmit FIFO empty bit */
#define SCI_TXFE                    0x00000002
/* SCI FIFO status register receive FIFO full bit */