lh7a404_sdmmc.h

在sharp 404开发板的串口测试代码

/***********************************************************************
 * $Workfile:   lh7a404_sdmmc.h  $
 * $Revision:   1.1  $
 * $Author:   WellsK  $
 * $Date:   Jul 01 2003 10:59:40  $
 *
 * Project: LH7A404 SD/MMC definitions
 *
 * Description:
 *     This file contains the structure definitions and manifest
 *     constants for the LH7A404 component:
 *         Secure Digital and Multi-Media Card Controller
 *
 * Revision History:
 * $Log:   //smaicnt2/pvcs/VM/sharpmcu/archives/sharpmcu/software/csps/lh7a404/include/lh7a404_sdmmc.h-arc  $
 * 
 *    Rev 1.1   Jul 01 2003 10:59:40   WellsK
 * Changed to use abl_types instead of sma_types.
 * 
 *    Rev 1.0   Jun 30 2003 16:28:52   WellsK
 * Initial revision.
 * 
 * 
 ***********************************************************************
 * SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION
 * OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE,
 * AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES, 
 * SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE.
 *
 * SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY 
 * FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A 
 * SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT. USE OF THIS SOURCE
 * FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS.
 *
 * COPYRIGHT (C) 2001 SHARP MICROELECTRONICS OF THE AMERICAS, INC.
 *     CAMAS, WA
 **********************************************************************/

#ifndef LH7A404_SDMMC_H
#define LH7A404_SDMMC_H

#include "abl_types.h"
#include "lh7a404_chip.h"

/***********************************************************************
 * SDMMC Module Register Structure
 **********************************************************************/

/* SDMMC Module Register Structure */ 
typedef struct 
{
    volatile UNS_32 clock_control; /* SDMMC Clock control register */ 
    volatile UNS_32 status;        /* SDMMC Controller status reg */ 
    volatile UNS_32 clock_rate;    /* SDMMC clock divider register */
    volatile UNS_32 clock_prediv;  /* SDMMC clock pre-divider reg */
    volatile UNS_32 spi;           /* SDMMC SPI mode control reg */
    volatile UNS_32 cmd_control;   /* SDMMC Command control reg */
    volatile UNS_32 response_to;   /* SDMMC Response timeout reg */
    volatile UNS_32 read_to;       /* SDMMC Read timeout register */
    volatile UNS_32 block_len;     /* SDMMC Block length register */
    volatile UNS_32 block_count;   /* SDMMC Block count register */ 
    volatile UNS_32 int_status;    /* SDMMC Interrupt status reg */
    volatile UNS_32 int_clear;     /* SDMMC Interrupt clear reg */ 
    volatile UNS_32 reserved1;
    volatile UNS_32 int_enable;    /* SDMMC Interrupt enable register */
    volatile UNS_32 command;       /* SDMMC Command Number register */
    volatile UNS_32 argument;      /* SDMMC Command Argument register */
    volatile UNS_32 response_fifo; /* SDMMC Response FIFO register */
    volatile UNS_32 reserved2;
    volatile UNS_32 data_fifo;     /* SDMMC Data FIFO register */
    volatile UNS_32 buf_part_full; /* SDMMC part buf for stream mode */
} SDMMC_REGS_T;

/***********************************************************************
 * SDMMC clock start/stop register definitions
 **********************************************************************/

/* SDMMC clock start/stop register stop clock bit */
#define MMC_CTRL_STOP_CLK                0x00000001
/* SDMMC clock start/stop register start clock bit */
#define MMC_CTRL_START_CLK               0x00000002

/***********************************************************************
 * MMC status register definitions
 **********************************************************************/

/* SDMMC status register read timeout bit */
#define MMC_STATUS_READ_TO               0x00000001
/* SDMMC status register response timeout bit */
#define MMC_STATUS_RESPONSE_TO           0x00000002
/* SDMMC status register CRC write error bit */
#define MMC_STATUS_CRC_ERROR_WRITE       0x00000004
/* SDMMC status register CRC read error bit */
#define MMC_STATUS_CRC_ERROR_READ        0x00000008
/* SDMMC status register SPI read error token bit */
#define MMC_STATUS_SPI_READ_ERROR_TOKEN  0x00000010
/* SDMMC status register response CRC error bit */
#define MMC_STATUS_CRC_ERROR_RESPONSE    0x00000020
/* SDMMC status register FIFO empty bit */
#define MMC_STATUS_FIFO_EMPTY            0x00000040
/* SDMMC status register FIFO full bit */
#define MMC_STATUS_FIFO_FULL             0x00000080
/* SDMMC status register clock enabled bit */
#define MMC_STATUS_CLOCK_ENABLED         0x00000100
/* SDMMC status register data transfer done bit */
#define MMC_STATUS_DATA_TRANSFER_DONE    0x00000800
/* SDMMC status register program done bit */
#define MMC_STATUS_PROGRAM_DONE          0x00001000
/* SDMMC status register command response complete bit */
#define MMC_STATUS_END_COMMAND_RESPONSE  0x00002000

/***********************************************************************
 * SDMMC clock rate register definitions
 **********************************************************************/

/* SDMMC clock rate register load macro */
#define MMC_CLOCK_RATE(n)                _SBF(0, ((n) & 0x7))
/* SDMMC clock rate register divide by 1 load value */
#define MMC_CLOCK_DIV1                   0
/* SDMMC clock rate register divide by 2 load value */
#define MMC_CLOCK_DIV2                   1
/* SDMMC clock rate register divide by 4 load value */
#define MMC_CLOCK_DIV4                   2
/* SDMMC clock rate register divide by 8 load value */
#define MMC_CLOCK_DIV8                   3
/* SDMMC clock rate register divide by 16 load value */
#define MMC_CLOCK_DIV16                  4
/* SDMMC clock rate register divide by 32 load value */
#define MMC_CLOCK_DIV32                  5
/* SDMMC clock rate register divide by 64 load value */
#define MMC_CLOCK_DIV64                  6

/***********************************************************************
 * SDMMC clock predivide register definitions
 **********************************************************************/

/* SDMMC clock predivide register load macro */
#define MMC_PREDIV(n)                    _SBF(0, ((n) & 0xF))
/* SDMMC clock predivide MMC clock gate bit */
#define MMC_PREDIV_EN                     0x00000010
/* SDMMC clock predivide APB read enable bit */
#define MMC_PREDIV_APB_RD_EN              0x00000020

/***********************************************************************
 * SDMMC SPI register definitions
 **********************************************************************/

/* SDMMC SPI register SPI mode enable bit */
#define MMC_SPI_EN                        0x00000001
/* SDMMC SPI register CRC mode enable bit */
#define MMC_SPI_CRC_ON                    0x00000002
/* SDMMC SPI register SPI chip select enable bit */
#define MMC_SPI_CS_EN                     0x00000004
/* SDMMC SPI register SPI chip select address 1 bit */
#define MMC_SPI_CS_ADDR                   0x00000008

/***********************************************************************
 * SDMMC command/data register definitions
 **********************************************************************/

/* SDMMC command/data register response format none value */
#define MMC_CMD_RESPONSE_NONE             _SBF(0, ((n) & 0x0))
/* SDMMC command/data register response format R1 value */
#define MMC_CMD_RESPONSE_R1               _SBF(0, ((n) & 0x1))
/* SDMMC command/data register response format R2 value */
#define MMC_CMD_RESPONSE_R2               _SBF(0, ((n) & 0x2))
/* SDMMC command/data register response format R3 value */
#define MMC_CMD_RESPONSE_R3               _SBF(0, ((n) & 0x3))
/* SDMMC command/data register data enable bit */
#define MMC_CMD_DATA_EN                   0x00000004
/* SDMMC command/data register write enable bit */
#define MMC_CMD_WRITE                     0x00000008
/* SDMMC command/data register stream enable bit */
#define MMC_CMD_STREAM                    0x00000010
/* SDMMC command/data register busy signal expectation bit */
#define MMC_CMD_BUSY                      0x00000020
/* SDMMC command/data register initialize enable bit */
#define MMC_CMD_INITIALIZE                0x00000040
/* SDMMC command/data register SD wide mode enable bit */
#define MMC_CMD_WIDE                      0x00000080
/* SDMMC command/data register big endian mode enable bit */
#define MMC_CMD_BIG_ENDIAN                0x00000100

/***********************************************************************
 * SDMMC response timeout register definitions
 **********************************************************************/

/* SDMMC response timeout register load macro */
#define MMC_RESPONSE_TO(n)                ((n) & 0x0000007F)

/***********************************************************************
 * SDMMC read timeout register definitions
 **********************************************************************/

/* SDMMC read timeout register load macro */
#define MMC_READ_TO(n)                    ((n) & 0x0000FFFF)

/***********************************************************************
 * SDMMC block length register definitions
 **********************************************************************/

/* SDMMC block length register load macro */
#define MMC_BLOCK_LEN(n)                  ((n) & 0x000003FF)

/***********************************************************************
 * SDMMC block count register definitions
 **********************************************************************/

/* SDMMC block count register load macro */
#define MMC_BLOCK_COUNT(n)                ((n) & 0x0000FFFF)

/***********************************************************************
 * SDMMC interrupt register definitions
 **********************************************************************/

/* SDMMC interrupt register data transfer done bit */
#define MMC_INT_DATA_TRANSFER_DONE        0x00000001
/* SDMMC interrupt register program done bit */
#define MMC_INT_PROGRAM_DONE              0x00000002
/* SDMMC interrupt register end command bit */
#define MMC_INT_END_CMD_RESPONSE          0x00000004
/* SDMMC interrupt register buffer ready bit */
#define MMC_INT_BUFFER_READY              0x00000008
/* SDMMC interrupt register bus clock stopped bit */
#define MMC_INT_CLOCK_DISABLED            0x00000010

/***********************************************************************
 * SDMMC command number register definitions
 **********************************************************************/
                                          
/* SDMMC command number register load macro */
#define MMC_CMD_NUM(n)                    _SBF(0, ((n) & 0x3F))

/***********************************************************************
 * SDMMC buffer partially full register definitions
 **********************************************************************/

/* SDMMC buffer partially full register partial FIFO written bit */
#define MMC_BUF_PART_FULL                 0x00000001

/* Macro pointing to interrupt controller registers */
#define SDMMC ((SDMMC_REGS_T *)(SDMMC_BASE))

#endif /* LH7A404_SDMMC_H */