sdk7a404_startup.h

在sharp 404开发板的串口测试代码

/***********************************************************************
 * $Workfile:   sdk7a404_startup.h  $
 * $Revision:   1.0  $
 * $Author:   WellsK  $
 * $Date:   Jul 01 2003 12:12:10  $
 *
 * Project: LogicPD SDKA404 startup code
 *
 * Description:
 *     This package contains the startup functions that initialize the
 *     SDKA404 EVB into a known state.
 *
 * Revision History:
 * $Log:   //smaicnt2/pvcs/VM/sharpmcu/archives/sharpmcu/software/csps/lh7a404/bsps/sdk7a404/startup/sdk7a404_startup.h-arc  $
 * 
 *    Rev 1.0   Jul 01 2003 12:12:10   WellsK
 * Initial revision.
 * 
 *
 ***********************************************************************
 * SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION
 * OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE,
 * AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES, 
 * SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE.
 *
 * SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY 
 * FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A 
 * SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT. USE OF THIS SOURCE
 * FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS.
 *
 * COPYRIGHT (C) 2001 SHARP MICROELECTRONICS OF THE AMERICAS, INC.
 *     CAMAS, WA
 **********************************************************************/

#ifndef SDK7A404_STARTUP_H
#define SDK7A404_STARTUP_H

#ifdef __cplusplus
extern "C" {
#endif

/***********************************************************************
 * Startup code defines and organization - this area defines the layout
 * memory used by the startup code. The defines here specify how the
 * stack and MMU page table are located in memory. Note that the stacks
 * are setup in the assembly code file (sdk7a404_startup_entry) and are
 * mirrored in that file. When making changes to the stack layout, be
 * sure to change that file also.
 **********************************************************************/

#define INITIAL_STK_ADDR    0xB0013FFC /* Initial stack address */

/* Location of MMU page table - this MUST be aligned of a 32K
   boundary and must be a physical address - located at the end of
   SDRAM */
#define MMU_TRANS_TAB_ADDR  0xCD3E0000
#define MMU_TRANS_TAB_SIZE  0x20000

/* FIQ mode stack address after MMU is enabled */
#define MMU_FIQ_STK_ADDR    (0x02000000 - MMU_TRANS_TAB_SIZE)
#define MMU_FIQ_STK_SIZE    0x400      /* FIQ mode stack size */

/* IRQ mode stack address after MMU is enabled */
#define MMU_IRQ_STK_ADDR    (MMU_FIQ_STK_ADDR - MMU_FIQ_STK_SIZE)
#define MMU_IRQ_STK_SIZE    0x800      /* IRQ mode stack size */

/* Abort mode stack address after MMU is enabled */
#define MMU_ABT_STK_ADDR    (MMU_IRQ_STK_ADDR - MMU_IRQ_STK_SIZE)
#define MMU_ABT_STK_SIZE    0x400      /* Abort mode stack size */

/* Exception stack address after MMU is enabled */
#define MMU_UND_STK_ADDR    (MMU_ABT_STK_ADDR - MMU_ABT_STK_SIZE)
#define MMU_UND_STK_SIZE    0x400      /* Exception stack size */

/* SYS mode stack address after MMU is enabled */
#define MMU_SYS_STK_ADDR    (MMU_UND_STK_ADDR - MMU_UND_STK_SIZE)
#define MMU_SYS_STK_SIZE    0x800      /* SYS mode stack size */

/* SVC mode stack address after MMU is enabled */
#define MMU_SVC_STK_ADDR    (MMU_SYS_STK_ADDR - MMU_SYS_STK_SIZE)
#define MMU_SVC_STK_SIZE    0x4000     /* SVC mode stack size */

/* MMU page definition table */
extern TT_SECTION_BLOCK_T tt_init_basic[];

/* Load regions and sizes */
#ifdef __GNUC__
extern UNS_32 __gnu_textstart;
extern UNS_32 __gnu_textend;
extern UNS_32 __gnu_datastart;
extern UNS_32 __gnu_dataend;
extern UNS_32 __gnu_bssstart;
extern UNS_32 __gnu_bssend;

/* Location of read-only image to copy (base address) */
#define RO_IMG_COPY_BASE  (UNS_32) &__gnu_textstart
/* Size of read-only image to copy */
#define RO_IMG_COPY_SIZE  (UNS_32) ((UNS_32) &__gnu_textend - \
                                    (UNS_32) &__gnu_textstart)
/* Location of where the RO image is loaded */
#define RO_LOAD_COPY_BASE (UNS_32) &__gnu_textstart
/* Location of read-write image (base address) */
#define RW_IMG_COPY_BASE  (UNS_32) &__gnu_datastart
/* Size of read-write image (base address) */
#define RW_IMG_COPY_SIZE  (UNS_32) ((UNS_32) &__gnu_dataend - \
                                    (UNS_32) &__gnu_datastart)
/* Location of where the read-write image is loaded (this will need
   to be copied to the RW_IMG_COPY_BASE) */
#define RW_LOAD_COPY_BASE (UNS_32) &__gnu_datastart
/* Location of read-only image to copy (base address) */
#define ZI_IMG_BASE       (UNS_32) &__gnu_bssstart
/* Size of read-only image to copy */
#define ZI_IMG_SIZE       (UNS_32) ((UNS_32) &__gnu_bssend - \
                                    (UNS_32) &__gnu_bssstart)

#else
#ifdef __ghs__ /* GHS linker symbols */
extern UNS_32 __ghsbegin_arm922t_reset;
extern UNS_32 __ghsend_secinfo;
extern UNS_32 __ghsbegin_pidbase;
extern UNS_32 __ghsend_data;
extern UNS_32 __ghsbegin_bss;
extern UNS_32 __ghsend_bss;

/* Location of read-only image to copy (base address) */
#define RO_IMG_COPY_BASE  (UNS_32) (&__ghsbegin_arm922t_reset)
/* Size of read-only image to copy */
#define RO_IMG_COPY_SIZE  (UNS_32) ((UNS_32) &__ghsend_secinfo - \
                                    (UNS_32) &__ghsbegin_arm922t_reset)
/* Location of where the RO image is loaded */
#define RO_LOAD_COPY_BASE (UNS_32) (&__ghs_begin_text)
/* Location of read-write image (base address) */
#define RW_IMG_COPY_BASE  (UNS_32) (&__ghsbegin_pidbase)
/* Size of read-write image (base address) */
#define RW_IMG_COPY_SIZE  (UNS_32) ((UNS_32) &__ghsend_data - \
                                    (UNS_32) &__ghsbegin_pidbase)
/* Location of where the read-write image is loaded (this will need
   to be copied to the RW_IMG_COPY_BASE) */
#define RW_LOAD_COPY_BASE (UNS_32) (&__ghsbegin_pidbase)
/* Location of read-only image to copy (base address) */
#define ZI_IMG_BASE       (UNS_32) (&__ghsbegin_bss)
/* Size of read-only image to copy */
#define ZI_IMG_SIZE       (UNS_32) ((UNS_32) &__ghsend_bss - \
                                    (UNS_32) &__ghsbegin_bss)

#else /* ARM linker symbols */
extern UNS_32 Image$$ER_RO$$Base;
extern UNS_32 Image$$ER_RO$$Length;
extern UNS_32 Load$$ER_RO$$Base;
extern UNS_32 Image$$ER_RW$$Base;
extern UNS_32 Image$$ER_RW$$Length;
extern UNS_32 Load$$ER_RW$$Base;
extern UNS_32 Image$$ER_ZI$$ZI$$Base;
extern UNS_32 Image$$ER_ZI$$ZI$$Length;

/* Location of read-only image to copy (base address) */
#define RO_IMG_COPY_BASE  (UNS_32) (&Image$$ER_RO$$Base)
/* Size of read-only image to copy */
#define RO_IMG_COPY_SIZE  (UNS_32) (&Image$$ER_RO$$Length)
/* Location of where the RO image is loaded */
#define RO_LOAD_COPY_BASE (UNS_32) (&Load$$ER_RO$$Base)
/* Location of read-write image (base address) */
#define RW_IMG_COPY_BASE  (UNS_32) (&Image$$ER_RW$$Base)
/* Size of read-write image (base address) */
#define RW_IMG_COPY_SIZE  (UNS_32) (&Image$$ER_RW$$Length)
/* Location of where the read-write image is loaded (this will need
   to be copied to the RW_IMG_COPY_BASE) */
#define RW_LOAD_COPY_BASE (UNS_32) (&Load$$ER_RW$$Base)
/* Location of read-only image to copy (base address) */
#define ZI_IMG_BASE       (UNS_32) (&Image$$ER_ZI$$ZI$$Base)
/* Size of read-only image to copy */
#define ZI_IMG_SIZE       (UNS_32) (&Image$$ER_ZI$$ZI$$Length)
#endif
#endif

/***********************************************************************
 * Startup code support functions
 **********************************************************************/

/* Main startup code entry point, called from reset entry code */
void sdk7a404_init(void);

/* Memory interfaces initialization */
void sdk7a404_memory_init(void);

/* SDRAM initialization */
void sdk7a404_sdram_init(void);

/* SDRAM refresh frequency update function */
void sdk7a404_sdram_refresh_update(UNS_32 new_bus_clock);

/* MMU initialization */
void sdk7a404_mmu_init(void);

#ifdef __cplusplus
}
#endif

#endif /* SDK7A404_STARTUP_H */