if_le_pci.c

很好的一个嵌入式linux平台下的bootloader

	struct pci_attach_args *pa = aux;

	if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD)
		return (0);

	switch (PCI_PRODUCT(pa->pa_id)) {
	case PCI_PRODUCT_AMD_PCNET_PCI:
	case PCI_PRODUCT_AMD_PCHOME_PCI:
		return (1);
	}

	return (0);
}

void
le_pci_attach(parent, self, aux)
	struct device *parent, *self;
	void *aux;
{
	struct le_softc *lesc = (void *)self;
	struct am7990_softc *sc = &lesc->sc_am7990;
	struct pci_attach_args *pa = aux;
#ifdef PROM
	vm_offset_t iobase;
	vm_offset_t paiobase;
#else
	pci_intr_handle_t ih;
	bus_addr_t iobase;
	bus_size_t iosize;
	bus_space_handle_t ioh;
	bus_space_tag_t iot = pa->pa_iot;
	pci_chipset_tag_t pc = pa->pa_pc;
#endif
	pcireg_t csr;
	int i;
	const char *intrstr;

	switch (PCI_PRODUCT(pa->pa_id)) {
	case PCI_PRODUCT_AMD_PCNET_PCI:
		lesc->sc_rap = PCNET_PCI_RAP;
		lesc->sc_rdp = PCNET_PCI_RDP;
		lesc->sc_bdp = PCNET_PCI_BDP;
		break;
	}

#ifdef PROM
	if (pci_map_io (pa->pa_tag, PCI_CBIO, &iobase, &paiobase)) {
		printf(": can't find I/O base\n");
		return;
	}
#else
	if (pci_io_find(pc, pa->pa_tag, PCI_CBIO, &iobase, &iosize)) {
		printf(": can't find I/O base\n");
		return;
	}
	if (bus_space_map(iot, iobase, iosize, 0, &ioh)) {
		printf(": can't map I/O space\n");
		return;
	}
#endif

#ifdef PROM	
	lesc->sc_iobase = iobase;
#ifdef DWIO
	/* do switch to 32-bit mode (for 5230!) */
	le_pci_wrcsr (sc, 0, 0);
#endif
	if ((le_pci_rdbcr (sc, 19) & ((1<<15)|(1<<14))) == 0) {
	    /* These are the bits that should be in EEROM */
	    unsigned short bits[64] = {
		0x4000, 0x05bc, 0xffff,	/* MAC address */
		0x0000,		/* CSR116 (On Now Misc. Configuration) */
		0x1100,		/* Hardware ID (MB 0x11); Reserved (MBZ) */
		0x1111,		/* Scratch */
		0x0270,		/* csum bytes 00-0b & 0e-0f */
		0x5757,		/* MB 0x5757 */
		0x0000,		/* BCR2 (Miscellaneous Configuration */
		0x00c0,		/* BCR4 Link Status LED = link up */
		0x0084,		/* BCR5 LED1 = Rx Activity */
		0x1080,		/* BCR6 LED2 = 100Mbs */
		0x0090,		/* BCR7 LED3 = Tx Activity */
		0x0000,		/* BCR9 Full-Duplex Control */
		0x9061,		/* BCR18 Burst & Bus Control */
		0x1818,		/* BCR22 PCI Latency */
		0x1022,		/* BCR23 PCI subsystem vendor */
		0x2000,		/* BCR24 PCI subsystem ID */
		0x0017,		/* BCR25 SRAM size */
		0x0008,		/* BCR26 SRAM boundary */
		0x0000,		/* BCR27 SRAM control */
		0x0000,		/* BCR32 MII CSR */
		0x03c0,		/* BCR33 MII address  */
		0x1022,		/* BCR35 PCI Vendor ID */
		0xfe11,		/* BCR36 PCI PMC */
		0x0114,		/* BCR37 PCI Data1  */
		0x010f,		/* BCR38 PCI Data2 */
		0x010f,		/* BCR39 PCI Data3 */
		0x010f,		/* BCR40 PCI Data4 */
		0x0114,		/* BCR41 PCI Data5 */
		0x010f,		/* BCR42 PCI Data6 */
		0x010f,		/* BCR43 PCI Data7 */
		0x010f,		/* BCR44 PCI Data8 */
		0x0000,		/* BCR48 MBZ */
		0x0000,		/* BCR49 MBZ */
		0x0000,		/* BCR50 MBZ */
		0x0000,		/* BCR51 MBZ */
		0x0000,		/* BCR52 MBZ */
		0x0000,		/* BCR53 MBZ */
		0x0000,		/* BCR54 MBZ */

		0x1900,		/* Checksum adjust byte; MBZ */

		/* Rest not used */
		0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
		0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
		0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff
	    };

	    /* patch ethaddr */
	    sbdethaddr (&bits[0]);

	    /* fix the checksum */
	    {
		int csum = 0;
		for (i = 0; i < 8; i++)
		{
		    if (i == 6)
			continue;
		    csum += bits[i] & 0xff;
		    csum += (bits[i] >> 8 ) & 0xff;
		}
		bits[6] = csum;
	    }
	    /* enable writes to LED regs & shadow RAM */
	    le_pci_wrbcr (sc, 2, (1<<12) | (1<<8));

	    /* copy first 16 bytes to address PROM space */
#ifdef DWIO
	    {
		volatile unsigned int *iob = (unsigned int *)iobase;
		unsigned int *bitsp = (unsigned int *)bits;
		for (i = 0; i < 4; i++) {
		    iob[i] = htorl(bitsp[i]);
		}
	    }
	    {
		unsigned short *iob = (unsigned short *)iobase;
		for (i = 0; i < 3; i++)
		    le_pci_wrcsr (sc, 12+i, bits[i]);
	    }
#else
	    {
		unsigned short *iob = (unsigned short *)iobase;
		for (i = 0; i < 8; i++) {
		    iob[i] = htols(bits[i]);
		    if (i < 3)
			le_pci_wrcsr (sc, 12+i, bits[i]);
		}
	    }
#endif

	    /* back to regular programming mode */
	    le_pci_wrcsr (sc, 116, bits[0x03]);
	    le_pci_wrbcr (sc, 4, bits[0x09]);
	    le_pci_wrbcr (sc, 5, bits[0x0a]);
	    le_pci_wrbcr (sc, 6, bits[0x0b]);
	    le_pci_wrbcr (sc, 7, bits[0x0c]);

	    le_pci_wrbcr (sc, 9, bits[0x0d]);

	    le_pci_wrbcr (sc, 18, bits[0x0e]);

	    le_pci_wrbcr (sc, 22, bits[0x0f]);
	    le_pci_wrbcr (sc, 23, bits[0x10]);
	    le_pci_wrbcr (sc, 24, bits[0x11]);
	    le_pci_wrbcr (sc, 25, bits[0x12]);
	    le_pci_wrbcr (sc, 26, bits[0x13]);
	    le_pci_wrbcr (sc, 27, bits[0x14]);

	    le_pci_wrbcr (sc, 32, bits[0x15]);
	    le_pci_wrbcr (sc, 33, bits[0x16]);

	    le_pci_wrbcr (sc, 35, bits[0x17]);
	    le_pci_wrbcr (sc, 36, bits[0x18]);
	    le_pci_wrbcr (sc, 37, bits[0x19]);
	    le_pci_wrbcr (sc, 38, bits[0x1a]);
	    le_pci_wrbcr (sc, 39, bits[0x1b]);
	    le_pci_wrbcr (sc, 40, bits[0x1c]);
	    le_pci_wrbcr (sc, 41, bits[0x1d]);
	    le_pci_wrbcr (sc, 42, bits[0x1e]);
	    le_pci_wrbcr (sc, 43, bits[0x1f]);
	    le_pci_wrbcr (sc, 44, bits[0x20]);

	    le_pci_wrbcr (sc, 48, bits[0x21]);
	    le_pci_wrbcr (sc, 49, bits[0x22]);
	    le_pci_wrbcr (sc, 50, bits[0x23]);
	    le_pci_wrbcr (sc, 51, bits[0x24]);
	    le_pci_wrbcr (sc, 52, bits[0x25]);
	    le_pci_wrbcr (sc, 53, bits[0x26]);
	    le_pci_wrbcr (sc, 54, bits[0x27]);
	    
	    /* finally write BCR2 */
	    le_pci_wrbcr (sc, 2, bits[0x08]);
		
	}
#endif

	/*
	 * Extract the physical MAC address from the ROM.
	 */
#ifdef PROM
	{
	    unsigned char *iob = (unsigned char *)iobase;
#if #endian(big) && defined(P6032)
	    for (i = 0; i < sizeof(sc->sc_arpcom.ac_enaddr); i++)
		sc->sc_arpcom.ac_enaddr[i] = iob[i^3];
#else
	    for (i = 0; i < sizeof(sc->sc_arpcom.ac_enaddr); i++)
		sc->sc_arpcom.ac_enaddr[i] = iob[i];
#endif
	}
#else
	for (i = 0; i < sizeof(sc->sc_arpcom.ac_enaddr); i++)
		sc->sc_arpcom.ac_enaddr[i] = bus_space_read_1(iot, ioh, i);
#endif

	sc->sc_mem = malloc(16384, M_DEVBUF, M_NOWAIT);
	if (sc->sc_mem == 0) {
		printf(": couldn't allocate memory for card\n");
		return;
	}
#ifdef __mips__
	sc->sc_mem = PA_TO_KVA1(KVA_TO_PA(sc->sc_mem));
#endif

#ifndef PROM
	printf("\n");

	lesc->sc_iot = iot;
	lesc->sc_ioh = ioh;
#endif

	sc->sc_conf3 = 0;
#ifdef PROM
	sc->sc_conf3 |= 1 << 6;		/* set DXSUFLO */
#endif
	sc->sc_addr = vtophys(sc->sc_mem);	/* XXX XXX XXX */
	sc->sc_memsize = 16384;

	sc->sc_copytodesc = am7990_copytodesc_contig;
	sc->sc_copyfromdesc = am7990_copyfromdesc_contig;
	sc->sc_copytobuf = am7990_copytobuf_contig;
	sc->sc_copyfrombuf = am7990_copyfrombuf_contig;
	sc->sc_zerobuf = am7990_zerobuf_contig;

	sc->sc_rdcsr = le_pci_rdcsr;
	sc->sc_wrcsr = le_pci_wrcsr;
	sc->sc_hwreset = NULL;
	sc->sc_hwinit = NULL;

#ifndef PROM
	printf("%s", sc->sc_dev.dv_xname);
#endif
	am7990_config(sc);

#ifdef PROM
	/* Enable the card. */
	csr = pci_conf_read(pa->pa_tag, PCI_COMMAND_STATUS_REG);
	pci_conf_write(pa->pa_tag, PCI_COMMAND_STATUS_REG,
	    csr | PCI_COMMAND_MASTER_ENABLE);
#else
	/* Enable the card. */
	csr = pci_conf_read(pc, pa->pa_tag,
	    PCI_COMMAND_STATUS_REG);
	pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
	    csr | PCI_COMMAND_MASTER_ENABLE);

	/* Map and establish the interrupt. */
	if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin,
	    pa->pa_intrline, &ih)) {
		printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname);
		return;
	}
	intrstr = pci_intr_string(pc, ih);
	lesc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, am7990_intr, sc,
	    sc->sc_dev.dv_xname);
	if (lesc->sc_ih == NULL) {
		printf("%s: couldn't establish interrupt",
		    sc->sc_dev.dv_xname);
		if (intrstr != NULL)
			printf(" at %s", intrstr);
		printf("\n");
		return;
	}
	printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr);
#endif
}