solo-defaults.tcl

一个用在mips体系结构中的操作系统

#
# Copyright (C) 1996-1998 by the Board of Trustees
#    of Leland Stanford Junior University.
# 
# This file is part of the SimOS distribution. 
# See LICENSE file for terms of the license. 
#

########################################################################
#                                                                      #
# Default parameter values for solo. This file should be sourced at    #
# the start of your init.solo file and then you can change any of the  #
# values below that source.                                            #
#                                                                      #
########################################################################

#
# MACHINES:
#
    # Number of machines to simulate
    set PARAM(MACHINE.Count)    1

#
# CPU:
#
    # Which instruction set architecture... currently only MIPS
    set PARAM(CPU.ISA)            "MIPS"

    # Default to R4000 (TLB) also support R10000
    set PARAM(TLB.Org)            R4000

    # Clock speed in MHz. 
    set PARAM(CPU.Clock)          200

    # CPU model -- solo always uses mipsy
    set PARAM(CPU.Model)          MIPSY
  
    # Number of CPUs
    set PARAM(CPU.Count)          1

#
# CACHE:
# 
#   2Level is currently the only type of cache model we support. 2Level
#   consists of separate level 1 instruction and data caches and a
#   unified level 2 cache. Additionally, there is a configurable write buffer.  
# 
    set PARAM(CACHE.Model)      2Level

  # 
  # 2Level specifics
  #
    # Size (in kilobytes) of the 1st level instruction cache
    set PARAM(CACHE.2Level.ISize)   32
    # Size (in bytes) of a 1st level instruction cache line
    set PARAM(CACHE.2Level.ILine)   64
    # Associativity of 1st level instruction cache
    set PARAM(CACHE.2Level.IAssoc)   2

    # Size (in kilobytes) of the 1st level data cache
    set PARAM(CACHE.2Level.DSize)   32    
    # Size (in bytes) of a 1st level data cache line
    set PARAM(CACHE.2Level.DLine)   64
    # Associativity of 1st level data cache
    set PARAM(CACHE.2Level.DAssoc)   2

    # Size (in kilobytes) of the 2nd level unified cache
    set PARAM(CACHE.2Level.L2Size)  1024
    # Size (in bytes) of a 2nd level cache line
    set PARAM(CACHE.2Level.L2Line)   128
    # Associativity of 2nd level unified cache
    set PARAM(CACHE.2Level.L2Assoc)     2

    # Time (in nanoseconds) for a 2nd level cache hit
    set PARAM(CACHE.2Level.L2HitTime)        50

    # The write buffer allows non-blocking writes. 0 turns off the buffer.
    set PARAM(CACHE.2Level.WriteBufferSize) 0

    # 
    set PARAM(CACHE.2Level.UpgradesOnUP)    0

    # Time (in *cycles*) before a NAKed memory request is retried
    set PARAM(CACHE.2Level.NAKRetryTime)    1

#
# MEMORY SYSTEM:
# 
#   Models include:
#   * BusUma     - uniform memory access time with bus contention,
#                  snoopy caches, writeback buffers, and an 
#                  out-of-order split transaction bus.
#   * Numa       - Similar to BusUma, but with latencies dependent on
#                  where memory is found.
#   * Perfect    - Models a zero access time memory system
#   * Flashlite  - Cycle accurate model of the FLASH memory system
#

    # Memory size in megabytes
    set PARAM(MEMSYS.MemSize)  32

    set PARAM(MEMSYS.Model)              BusUma

 
    set PARAM(MEMSYS.Perfect.Latency) 0
 
 #
 # BusUma parameters
 #

    # The maximum bandwith (in MB/s) that the bus can support
    set PARAM(MEMSYS.BusUma.BusBW)         1200

    # Total time (in ns) to fetch a cache line from memory in an unloaded system
    set PARAM(MEMSYS.BusUma.MemCycleTime)   500

    # The time (in ns) to get data out of another CPU's cache if it is dirty there.
    # Overall time for a dirty miss will be (MemCycleTime + DirtyPenalty) 
    # in an unloaded system.   
    set PARAM(MEMSYS.BusUma.DirtyPenalty)   250

    # Total time (in ns) to issue an upgrade in an unloaded system.
    set PARAM(MEMSYS.BusUma.UpgradeTime)    400

    # The number of memory units (banks).  Different memories can be servicing
    # requests simultaneously if the requested data is in different memory units.
    set PARAM(MEMSYS.BusUma.NumMemories)      1


    #
    # Numa parameters
    #

    # The number of memories/directory controllers in the system. The
    # value should lie in the range of 1 to "NUM_CPUS". 1 would be 
    # like a bus-based system. "NUM_CPUS" would be a CPU per
    # controller (e.g. FLASH) and anything in between would have
    # clusters of CPUs per controller (e.g. DASH). 
    set PARAM(MEMSYS.Numa.NumMemories)        1 

    # The latency (in ns) for the bus operation from a processor to
    # its local directory controller.
    set PARAM(MEMSYS.Numa.BusTime)          100

    # The time (in ns) it takes the directory controller to do specific
    # operations.

    # PILocalDCTime = occupancy of dc on local miss
    set PARAM(MEMSYS.Numa.PILocalDCTime)     100

    # PIRemoteDCTime = occupancy of local dc on outgoing remote miss
    set PARAM(MEMSYS.Numa.PIRemoteDCTime)    25

    # NILocalDCTime = occupancy of remote dc on remote miss
    set PARAM(MEMSYS.Numa.NILocalDCTime)     350

    # NIRemoteDCTime = occupancy of local dc on incoming remote miss
    set PARAM(MEMSYS.Numa.NIRemoteDCTime)    25


    # Latency (in ns) for the directory controller to fetch a cache
    # line from local memory.
    set PARAM(MEMSYS.Numa.MemTime)           50

    # Fixed latency (in ns) for going between directory controllers,
    # across the network. 
    set PARAM(MEMSYS.Numa.NetTime)          350

    # Granularity (in pages) of striping physical pages across
    # directory controllers. For example, if this is set to 1, memory
    # pages are distributed roundrobin across the cotrollers. The  
    # default (-1) is stripe size of
    # PARAM(MEMSYS.MemSize)/PARAM(MEMSYS.Numa.NumMemories)/PAGE_SIZE. 
    set PARAM(MEMSYS.Numa.StripeSize)       -1

# 
# FILES:
# 
    # If this is set, cpu log files will be saved as cpu.log.<number>
    set PARAM(FILES.SaveOldCPULogs) yes

#
# VISUAL:
#
    # The port to which the SimOS visual interface should connect
    set PARAM(VISUAL.Port)           1865

    # Period in cycles in which SimOS checks the visual interface
    set PARAM(VISUAL.SamplePeriod)   4194304