ms_compile.c

一个用在mips体系结构中的操作系统

/*
 * Copyright (C) 1996-1998 by the Board of Trustees
 *    of Leland Stanford Junior University.
 * 
 * This file is part of the SimOS distribution. 
 * See LICENSE file for terms of the license. 
 *
 */


	/*
	 *  ms_compile  -  Compile a single MIPS instruction into an
	 *		   instruction that the MXS simulator can deal with.
	 *
	 *	Jim Bennett
	 *	1993, 1994, 1995
	 */

#include <stdlib.h>
#include "ms.h"
#include "mc.h"

int mc_spec (uint inst, uint addr, INST *ip);
int mc_regimm (uint inst, uint addr, INST *ip);
int mc_cop1 (uint inst, uint addr, INST *ip);
void mc_cop0 (uint inst, uint addr, INST *ip);
void mc_fp_s (uint inst, uint addr, INST *ip);
void mc_fp_d (uint inst, uint addr, INST *ip);


	/*
	 *  compile_inst  -  Fetch instruction at the given address and
	 *			compile it.
	 *
	 *	Returns indicators if the instruction was a no-op (squashed)
	 *	or a branch (branch_shadow)
	 */

void compile_inst (uint inst, uint addr, INST *ip,
			int *squashed, int *branch_shadow)
	{
	int	opc1;

	*squashed = 0;
	*branch_shadow = 0;
	opc1 = (inst >> 26) & 0x3f;
	switch (opc1)
		{
		case 0:				/* SPECIAL	*/
			if (inst == 0)
				*squashed = 1;
			*branch_shadow = mc_spec (inst, addr, ip);
			break;
		case 1:				/* REGIMM	*/
			*branch_shadow = mc_regimm (inst, addr, ip);
			break;

		case 2:
			ip->op = OPJ;
			ip->r1 = -1;
			ip->r2 = -1;
			ip->r3 = -1;
			ip->imm = ((addr+4) & 0xf0000000) |
					((inst & 0x3ffffff) << 2);
			*branch_shadow = 1;
			break;

		case 3:
			ip->op = OPJAL;
			ip->r1 = LP;
			ip->r2 = -1;
			ip->r3 = -1;
			ip->imm = ((addr+4) & 0xf0000000) |
					((inst & 0x3ffffff) << 2);
			*branch_shadow = 1;
			break;

		case 4:
			ip->op = OPBEQ;
			ip->r1 = -1;
			ip->r2 = RTRI(inst);
			ip->r3 = RSRI(inst);
			ip->imm = (inst & 0x00008000 ?
		    (addr+4) - ((0x10000 - (inst&0x0000ffff)) << 2) :
				(addr+4) + ((inst&0x0000ffff) << 2) );
			*branch_shadow = 1;
			break;

		case 5:
			ip->op = OPBNE;
			ip->r1 = -1;
			ip->r2 = RTRI(inst);
			ip->r3 = RSRI(inst);
			ip->imm = (inst & 0x00008000 ?
		    (addr+4) - ((0x10000 - (inst&0x0000ffff)) << 2) :
				(addr+4) + ((inst&0x0000ffff) << 2) );
			*branch_shadow = 1;
			break;

		case 6:				/* BLEZ		*/
			ip->op = OPBLEZ;
			ip->r1 = -1;
			ip->r2 = RSRI(inst);
			ip->r3 = -1;
			ip->imm = (inst & 0x00008000 ?
		    (addr+4) - ((0x10000 - (inst&0x0000ffff)) << 2) :
				(addr+4) + ((inst&0x0000ffff) << 2) );
			*branch_shadow = 1;
			break;

		case 7:				/* BGTZ		*/
			ip->op = OPBGTZ;
			ip->r1 = -1;
			ip->r2 = RSRI(inst);
			ip->r3 = -1;
			ip->imm = (inst & 0x00008000 ?
		    (addr+4) - ((0x10000 - (inst&0x0000ffff)) << 2) :
				(addr+4) + ((inst&0x0000ffff) << 2) );
			*branch_shadow = 1;
			break;

		case 8:
			ip->op = OPADDI;
			ip->r1 = RTRI(inst);
			ip->r2 = RSRI(inst);
			ip->r3 = -1;
			ip->imm = IMMED(inst);
			break;

		case 9:
			ip->op = OPADDIU;
			ip->r1 = RTRI(inst);
			ip->r2 = RSRI(inst);
			ip->r3 = -1;
			ip->imm = IMMED(inst);
			break;

		case 10:
			ip->op = OPSLTI;
			ip->r1 = RTRI(inst);
			ip->r2 = RSRI(inst);
			ip->r3 = -1;
			ip->imm = IMMED(inst);
			break;

		case 11:
			ip->op = OPSLTIU;
			ip->r1 = RTRI(inst);
			ip->r2 = RSRI(inst);
			ip->r3 = -1;
			ip->imm = IMMED(inst);
			break;

		case 12:
			ip->op = OPANDI;
			ip->r1 = RTRI(inst);
			ip->r2 = RSRI(inst);
			ip->r3 = -1;
			ip->imm = inst & 0x0000ffff;
			break;

		case 13:
			ip->op = OPORI;
			ip->r1 = RTRI(inst);
			ip->r2 = RSRI(inst);
			ip->r3 = -1;
			ip->imm = inst & 0x0000ffff;
			break;

		case 14:
			ip->op = OPXORI;
			ip->r1 = RTRI(inst);
			ip->r2 = RSRI(inst);
			ip->r3 = -1;
			ip->imm = inst & 0x0000ffff;
			break;

		case 15:			/* LUI -> ORI	*/
			ip->op = OPORI;
			ip->r1 = RTRI(inst);
			ip->r2 = 0;
			ip->r3 = -1;
			ip->imm = inst << 16;
			break;

		case 16:			/* COP0		*/
			mc_cop0(inst, addr, ip);
			break;

		case 17:			/* COP1		*/
			*branch_shadow = mc_cop1 (inst, addr, ip);
			break;

		case 18:			/* COP2		*/
#ifdef PRINT_WARN
			fprintf (stderr,
				"Illegal instruction (COP2)\n");
#endif
			ip->r1 = ip->r2 = ip->r3 = -1;
			ip->op = OPILL;
			break;

		case 19:			/* COP3		*/
#ifdef PRINT_WARN
			fprintf (stderr,
				"Illegal instruction (COP3)\n");
#endif
			ip->r1 = ip->r2 = ip->r3 = -1;
			ip->op = OPILL;
			break;

		case 20:			/* BEQL		*/
			ip->op = OPBEQL;
			ip->r1 = -1;
			ip->r2 = RTRI(inst);
			ip->r3 = RSRI(inst);
			ip->imm = (inst & 0x00008000 ?
		    (addr+4) - ((0x10000 - (inst&0x0000ffff)) << 2) :
				(addr+4) + ((inst&0x0000ffff) << 2) );
			*branch_shadow = 1;
			break;

		case 21:			/* BNEL		*/
			ip->op = OPBNEL;
			ip->r1 = -1;
			ip->r2 = RTRI(inst);
			ip->r3 = RSRI(inst);
			ip->imm = (inst & 0x00008000 ?
		    (addr+4) - ((0x10000 - (inst&0x0000ffff)) << 2) :
				(addr+4) + ((inst&0x0000ffff) << 2) );
			*branch_shadow = 1;
			break;

		case 22:			/* BLEZL	*/
			ip->op = OPBLEZL;
			ip->r1 = -1;
			ip->r2 = RSRI(inst);
			ip->r3 = -1;
			ip->imm = (inst & 0x00008000 ?
		    (addr+4) - ((0x10000 - (inst&0x0000ffff)) << 2) :
				(addr+4) + ((inst&0x0000ffff) << 2) );
			*branch_shadow = 1;
			break;

		case 23:			/* BGTZL	*/
			ip->op = OPBGTZL;
			ip->r1 = -1;
			ip->r2 = RSRI(inst);
			ip->r3 = -1;
			ip->imm = (inst & 0x00008000 ?
		    (addr+4) - ((0x10000 - (inst&0x0000ffff)) << 2) :
				(addr+4) + ((inst&0x0000ffff) << 2) );
			*branch_shadow = 1;
			break;

		/* 24-31 unused */

		case 32:
			ip->op = OPLB;
			ip->r1 = RTRI(inst);
			ip->r2 = RSRI(inst);
			ip->r3 = -1;
			ip->imm = IMMED(inst);
            break;

		case 33:
			ip->op = OPLH;
			ip->r1 = RTRI(inst);
			ip->r2 = RSRI(inst);
			ip->r3 = -1;
			ip->imm = IMMED(inst);
			break;

		case 34:
			ip->op = OPLWL;
			ip->r1 = RTRI(inst);
			ip->r2 = RSRI(inst);
			ip->r3 = RTRI(inst);
			ip->imm = IMMED(inst);
			break;

		case 35:
			ip->op = OPLW;
			ip->r1 = RTRI(inst);
			ip->r2 = RSRI(inst);
			ip->r3 = -1;
			ip->imm = IMMED(inst);
			if ((ip->r2 == 0) && (ip->r1 == 2) && (ip->imm == 3)) {
			   /* in SimOS direct exeception mode - lw v0,3($0) is a 
			    * system call */
			   ip->op = OPSYSCALL;
			   ip->r1 = -1;
			   ip->r2 = -1;
			   ip->r3 = -1;
			   ip->imm = 0;
			}
			break;

		case 36:
			ip->op = OPLBU;
			ip->r1 = RTRI(inst);
			ip->r2 = RSRI(inst);
			ip->r3 = -1;
			ip->imm = IMMED(inst);
			break;

		case 37:
			ip->op = OPLHU;
			ip->r1 = RTRI(inst);
			ip->r2 = RSRI(inst);
			ip->r3 = -1;
			ip->imm = IMMED(inst);
			break;

		case 38:
			ip->op = OPLWR;
			ip->r1 = RTRI(inst);
			ip->r2 = RSRI(inst);
			ip->r3 = RTRI(inst);
			ip->imm = IMMED(inst);
			break;

		/* 39 unused */

		case 40:
			ip->op = OPSB;
			ip->r1 = -1;
			ip->r2 = RSRI(inst);
			ip->r3 = RTRI(inst);
			ip->imm = IMMED(inst);
			break;

		case 41:
			ip->op = OPSH;
			ip->r1 = -1;
			ip->r2 = RSRI(inst);
			ip->r3 = RTRI(inst);
			ip->imm = IMMED(inst);
			break;

		case 42:
			ip->op = OPSWL;
			ip->r1 = -1;
			ip->r2 = RSRI(inst);
			ip->r3 = RTRI(inst);
			ip->imm = IMMED(inst);
			break;

		case 43:
			ip->op = OPSW;
			ip->r1 = -1;
			ip->r2 = RSRI(inst);
			ip->r3 = RTRI(inst);
			ip->imm = IMMED(inst);
			break;

		/* 44, 45 unused */

		case 46:
			ip->op = OPSWR;
			ip->r1 = -1;
			ip->r2 = RSRI(inst);
			ip->r3 = RTRI(inst);
			ip->imm = IMMED(inst);
			break;

		case 47:			/* CACHE	*/
			ip->op = OPCP0;
                        ip->r1 = -1;
                        ip->r2 = RSRI(inst);
                        ip->r3 = -1;
                        ip->imm = inst;
			break;

		case 48:			/* LL		*/
			ip->op = OPLL;
			ip->r1 = RTRI(inst);
			ip->r2 = RSRI(inst);
			ip->r3 = -1;
			ip->imm = IMMED(inst);
			break;

		case 49:
			ip->op = OPLWC1;
			ip->r1 = FTRI(inst);
			ip->r2 = RSRI(inst);
			ip->r3 = -1;
			ip->imm = IMMED(inst);
			break;

		case 50:			/* LWC2		*/
#ifdef PRINT_WARN
			fprintf (stderr,
				"LWC2 instruction not supported\n");
			fprintf (stderr, "Location: 0x%8.8x\n", addr);
#endif
			ip->r1 = ip->r2 = ip->r3 = -1;
			ip->op = OPILL;
			break;


		case 51:			/* PREF		*/
            ip->op = OPPREF;
            /* RPB hack -- make hint field negative so it isn't treated as a register */
            ip->r1 = -RTRI(inst);
            ip->r2 = RSRI(inst);
            ip->r3 = -1;
            ip->imm = IMMED(inst);
			break;

		/* 52 unused */

		case 53:
			ip->op = OPLDC1;
			ip->r1 = DTRI(inst);
			ip->r2 = RSRI(inst);
			ip->r3 = -1;
			ip->imm = IMMED(inst);
			break;
		case 55:			/* LD		*/
#ifdef PRINT_WARN
                        fprintf (stderr, "Hacked LD instruction found\n");
#endif
		case 54:			/* LDC2		*/
                   /* This is not a real LD is the special hacked LD
                    * that allows us to commication with flashlite from
                    * the 32bit CPU model we are currently using 
                    */
			ip->r1 = ip->r2 = ip->r3 = -1;
			ip->op = OPLDHACK;
                        ip->imm = inst;
			break;

		case 56:			/* SC		*/
			ip->op = OPSC;
			ip->r1 = RTRI(inst);
			ip->r2 = RSRI(inst);
			ip->r3 = RTRI(inst);
			ip->imm = IMMED(inst);
			break;

		case 57:
			ip->op = OPSWC1;
			ip->r1 = -1;
			ip->r2 = RSRI(inst);
			ip->r3 = FTRI(inst);
			ip->imm = IMMED(inst);
			break;

		case 58:			/* SWC2		*/
#ifdef PRINT_WARN
			fprintf (stderr,
				"SWC2 instruction not supported\n");
			fprintf (stderr, "Location: 0x%8.8x\n", addr);
#endif
			ip->r1 = ip->r2 = ip->r3 = -1;
			ip->op = OPILL;
			break;

		case 59:			/* SWC3		*/
#ifdef PRINT_WARN
			fprintf (stderr,
				"SWC3 instruction not supported\n");
			fprintf (stderr, "Location: 0x%8.8x\n", addr);
#endif
			ip->r1 = ip->r2 = ip->r3 = -1;
			ip->op = OPILL;
			break;

		/* 60 unused */

		case 61:
			ip->op = OPSDC1;
			ip->r1 = -1;
			ip->r2 = RSRI(inst);
			ip->r3 = DTRI(inst);
			ip->imm = IMMED(inst);
			break;
		case 63:			/* SD		*/
#ifdef PRINT_WARN
                        fprintf (stderr, "Hacked LD instruction found\n");
#endif
		case 62:			/* SDC2		*/
                   /* This is not a real SD is the special hacked D
                    * that allows us to commication with flashlite from
                    * the 32bit CPU model we are currently using 
                    */
			ip->r1 = ip->r2 = ip->r3 = -1;
			ip->op = OPSDHACK;
                        ip->imm = inst;
			break;

		default:
#ifdef PRINT_WARN
			fprintf (stderr,
				"Illegal instruction (undefined)\n");
			fprintf (stderr, "Location: 0x%8.8x\n", addr);
#endif
			ip->r1 = ip->r2 = ip->r3 = -1;
			ip->op = OPILL;
			break;
		}
	}


	/*
	 *  mc_spec  -  Compile the SPECIAL opcodes
	 */

int mc_spec (uint inst, uint addr, INST *ip)
	{
	int branch_shadow = 0;

	switch (inst & 0x03f)
		{
		case 0:
			ip->op = OPSLL;
			ip->r1 = RDRI(inst);
			ip->r2 = RTRI(inst);
			ip->r3 = -1;
			ip->imm = SHAMT(inst);
			break;

		/* 1 unused */

		case 2:
			ip->op = OPSRL;
			ip->r1 = RDRI(inst);
			ip->r2 = RTRI(inst);
			ip->r3 = -1;
			ip->imm = SHAMT(inst);
			break;

		case 3:
			ip->op = OPSRA;
			ip->r1 = RDRI(inst);
			ip->r2 = RTRI(inst);
			ip->r3 = -1;
			ip->imm = SHAMT(inst);
			break;

		case 4:
			ip->op = OPSLLV;
			ip->r1 = RDRI(inst);
			ip->r2 = RTRI(inst);
			ip->r3 = RSRI(inst);
			ip->imm = 0;
			break;

		/* 5 unused */

		case 6:
			ip->op = OPSRLV;
			ip->r1 = RDRI(inst);
			ip->r2 = RTRI(inst);
			ip->r3 = RSRI(inst);
			ip->imm = 0;
			break;