ms.h

一个用在mips体系结构中的操作系统

#define	AddToStat(sttype,cnt)						\
	{ st->stats[0].stat_cycles[(sttype)] += (cnt);			\
	  if (st->stats[0].stat_cycles[(sttype)] >= TICK_COUNT)		\
		{ st->stats[0].stat_cycles[(sttype)] -= TICK_COUNT;	\
		st->stats[0].stat_ticks[(sttype)]++; } }

	/*
	 *  Define the conversion from the virtual address of the process
	 *  being simulated to the real address of the data (in the
	 *  simulator's address space).  Needed in order to make system
	 *  calls in behalf of the simulated process
	 */

#define	SIM_MEMORY(x) ((x) >= pmap.data_base ? \
			&pmap.data_buf [(x) - pmap.data_base] : \
			((x) >= pmap.text_base ? \
				&pmap.text_buf [(x) - pmap.text_base] : \
				(void *)(x)) )
#define	CPUNUM(st)		(0)
#define bp_pc_to_index(_pc) ((_pc)&(BP_TABLE_SIZE-1))

#endif /* MIPSY_MXS */


/************************************************************************/
/*									*/
/*		Simulated machine state					*/
/*									*/
/************************************************************************/

typedef	struct			/* Branch tree structure		*/
	{
	int	thread;			/* Thread number of this node	*/
	int	thread_st;		/* Thread status		*/
	int	lchild;			/* Indices of nodes children	*/
	int	rchild;
	int	condition;		/* How to resolve branch	*/
	int	resolution;
	int	indirect;		/* If indirect branch		*/
	int	jret;			/* If subroutine return		*/
	int	call;			/* If a call			*/
	int	uncond;			/* If immediate unconditional	*/
	int	restore;		/* If branch stack needs restore */
	int	iwin_head_th;		/* Chain of instructions for	*/
	int	iwin_tail_th;		/* this node.			*/
	} BrTREE;


struct	s_thread		/* Per thread of control state		*/
	{
	int	pc;			/* Program counter (per thread)	*/
	int	thread_st;		/* Thread status		*/
	int	stall_fetch;		/* If instruction fetch stalled	*/
	int	branch_dly;		/* In branch delay slot		*/
	int	branch_likely;		/* Ditto for branch likely inst's */
	int	stall_fpc;		/* If stall due to FP control write */
	int	stall_branch;		/* Stalled waiting for branch	*/
	int	stall_thread;		/* Stalled waiting for branch -	*/
					/* no free threads		*/
	int	stall_icache;		/* Problem fetching inst. from cache */
        int     icache_stall_reason;    /* Cause of icache stall */
	int	stall_except;		/* Stall due to exception	*/
	int	stall_itlbmiss;		/* Stall due to ITLB miss	*/
	int	stall_sys;		/* Stall due to system call	*/
	int	stall_sc;		/* Stall due to an SC		*/
	int	stall_cp0;		/* Stall due to an CP0 inst	*/
	int	returnpc;		/* Return address PC		*/
	int	branch_sp;		/* Branch stack pointer		*/
	int	old_prediction;		/* Previous value of branch stack */
	int	branch_inum;		/* Index of branch inst.	*/
	int	branch_node;		/* Index of branch tree node	*/
	int	branch_pc;		/* Branch target address	*/
	int	branch_likely_pc;	/* Ditto for branch likely inst's */
	int	except;			/* Type of exception		*/
	struct s_thread *active_thread;	/* Next active thread		*/
	int	debugpc;		/* User PC for debugging	*/
	int	regnames [MAX_VAR];	/* Register names, indexed by	*/
					/* logical register (from inst)	*/
	int	half_def [MAX_VAR/2];	/* Flags for double registers	*/
	};

typedef struct s_thread THREAD;

#define	TH_ACTIVE	0x01			/* If thread active	*/
#define	TH_SPEC		0x02			/* If thread speculative */
#define	TH_BRANCH	0x04			/* If branch graduated	*/

#define	UpdateStallFetch(th)	\
	(th)->stall_fetch = (th)->stall_fpc || (th)->stall_branch ||	\
		(th)->stall_icache || (th)->stall_except ||		\
		(th)->stall_itlbmiss || (th)->stall_sys ||		\
		(th)->stall_sc || (th)->stall_cp0

#define	REGNAME_MASK	0x0ffff
#define	REGNAME_CLAIM	0x10000


struct	s_regstat		/* Register state needed for fast	*/
	{			/* access:				*/
	int	reg_status;		/* Status flags			*/
	int	reg_ref;		/* Reference count for register	*/
	int	reg_nmap;		/* Map count for register	*/
	int	reg_nclaims;		/* Claim count for register	*/
	};

typedef	struct s_regstat REGSTAT;

#define	REG_BUSY	0x0001		/* Physical registers		*/
#define	REG_IN_WIN	0x0002
#define	REG_MAPPED	0x0004
#define	REG_DMAP	0x0008

#define	REG_ERROR	0x0010		/* Indicates a fault		*/
#define	REG_CLAIMED	0x0020		/* Reg belongs to thread	*/
#define	REG_FREED	0x0040		/* Reg should be freed		*/


	/*
	 *  MemCallback  -  This structure holds information about
	 *		    how to handle callbacks from the memory
	 *		    subsystem.
	 */

typedef	struct
	{
	int	next_cb;
	int	action;
	} MemCallback;

#define	ACT_NULL		0	/* Do nothing on callback	*/
#define	ACT_UNSTALL_ICACHE	1	/* Unstall icache on callback	*/
#define ACT_DCACHE_MISS		2	/* A dcache miss finishes	*/


struct	s_cpu_state		/* Holds all processor state.		*/
	{
	int	regs [MAX_PREG];	/* All of the machine registers	*/

	THREAD	threads [THREAD_WIDTH];	/* Threads of execution		*/
	THREAD	*active_thread;		/* First active thread		*/
	int	free_thread;		/* Free list for threads	*/
	int	nthreads;		/* Number of threads		*/
	int	nactive;		/* Number of active threads	*/

	BrTREE	branch_tree [2*THREAD_WIDTH]; /* Active branch tree	*/
	int	free_branch_node;	/* Free list for branch tree	*/

	int	round_mode;		/* FP rounding mode		*/
	int	stall_issue;		/* If instruction issue stalled	*/
	int	stall_type;		/* Reason for inst issue stall	*/
	int	wbacks;			/* Count of write backs this cycle */

		/* Physical register status	*/
	int	reg_owner [MAX_PREG];	/* Owner of this register	*/
	REGSTAT	reg_rstat [MAX_PREG/2];	/* Status of register		*/
	int	reg_excuse [MAX_PREG/2]; /* Reason why reg not yet available */
	int	new_excuse [MAX_PREG/2]; /* Yet another reason why reg ... */
	int	reg_freelist [MAX_PREG/2];
	int	reg_otherhalf2 [MAX_PREG/2]; /* Dependency on first def	*/
	int	reg_otherhalf3 [MAX_PREG/2]; /* carried by r2 or r3	*/
	int	reg_nextfree;

		/* Instruction window, handles dependencies between	*/
		/* instructions, and issues instructions out-of-order.	*/
		/* Includes instructions in execution also.		*/

	int	iwin_ninst;		/* Number of instructions in	*/
					/* window and not yet executing	*/
	INST	iwin [TOTAL_INST];	/* Instruction window		*/
	int	iwin_addr [TOTAL_INST];	/* Address field for load/stores */
	int	iwin_paddr [TOTAL_INST]; /* paddr field for load/stores */
	int	iwin_flags [TOTAL_INST];
	int	iwin_freelist [TOTAL_INST];
					/* Instructions dependent on	*/
					/* this one.			*/
	int	iwin_dep2 [TOTAL_INST] [TOTAL_INST];
	int	iwin_dep3 [TOTAL_INST] [TOTAL_INST];
	int	iwin_index2 [TOTAL_INST];
	int	iwin_index3 [TOTAL_INST];
	int	iwin_pri [TOTAL_INST];	/* Priority chain for insts	*/
	int	iwin_bpri [TOTAL_INST];	/* Back pointers in chain	*/

#ifdef PRECISE
	THREAD	grad;			/* Thread state at graduation point */

	int	iwin_headgrad;		/* Head and tail of graduation queue */
	int	iwin_tailgrad;
	int	iwin_grad [TOTAL_INST];		/* Graduation queue	*/
	int	iwin_bgrd [TOTAL_INST];

	int	iwin_lr1 [TOTAL_INST];		/* Saved logical reg's	*/
	int	iwin_lr2 [TOTAL_INST];
	int	iwin_lr3 [TOTAL_INST];
#endif
	int	iwin_avail_list [TOTAL_INST];	/* Instructions ready	*/
						/* to be executed.	*/
	int	iwin_pc [TOTAL_INST];
#ifdef BREAKPOINT
	int	iwin_curi;
#endif
	int	iwin_nextfree;
	int	iwin_headpri;		/* Prioritized list of instructions */
	int	iwin_tailpri;
	int	iwin_next_avail;	/* Head and tail of available list */
	int	iwin_last_avail;

		/* Special support for speculative execution.		*/

	int	iwin_br_node [TOTAL_INST];	/* Branch tree node	*/
	int	iwin_thread [TOTAL_INST];	/* Thread inst chain	*/
	int	iwin_branch_pc [TOTAL_INST];	/* PC of branch target	*/
	int	iwin_bthread [TOTAL_INST];

		/* Support for memory callbacks into MXS		*/

	int	ms_action;		/* Action to take on callback	*/
					/* (index into callback table)	*/
	int	cb_free;
	MemCallback	callbacks [MAX_CALLBACK];

		/* Special support for load/store ordering.	*/

	int	iwin_ldst [TOTAL_INST];	/* Load/store chain		*/
	int	iwin_bldst [TOTAL_INST];
	int	iwin_head_ldst;
	int	iwin_tail_ldst;
	int	iwin_nldst;		/* Number of items in ldst chain */
#ifdef ONE_PHASE_LS
	int	iwin_nstores;
#endif

		/* Support for exceptions			*/

	int	iwin_except [TOTAL_INST];
	int	exception_pending;
	int	except;

		/* Branch prediction counters and addresses	*/

	int	bp_bits [BP_TABLE_SIZE];
	int	bp_targets [BP_TABLE_SIZE];
	int	branch_stack[BP_RETURN_STACK];
	int	branch_sp;

		/* Execution unit, pointers to executing instructions	*/

	int	ex [2*ISSUE_WIDTH];
	int	ex_count;

		/* Worklist mechanism, handles instruction completion	*/

	int	work_cycle;		/* Total cycles			*/
	int	work_ticks;		/* Total ticks (TICK_COUNT cycles) */

	WorkList *work_head;		/* Prioritized queue of time	*/
	WorkList *work_tail;		/* delayed work items (e.g.	*/
	WorkList *free_head;		/* FP operation write back,	*/
	WorkList *free_tail;		/* or memory load completion).	*/
	WorkList worklist [MAX_WORK_ITEMS];

		/* Load/store buffer, for the memory subsystem		*/

	struct s_ldst_buffer ldst_buffer[LDST_BUFFER_SIZE];
	struct	s_lsq	lsq [LDST_BUFFER_SIZE];
	struct s_ldst_buffer *ldst_nextAvail;
	struct s_ldst_buffer *ldst_nextReserved;
	struct s_ldst_buffer *ldst_head;
	struct s_ldst_buffer *ldst_tail;
	struct s_ldst_buffer *inum2ldst[TOTAL_INST];

		/* Cycle by cycle statistics				*/
        uint64 stats[NUM_MODES][ST_NTYPES];

               /* Sample stats */
        struct {
          uint64 samples;
          uint64 nthreads_hist[THREAD_WIDTH+1];
          uint64 reg_hist[MAX_PREG/2+1];
          struct {
              uint64 inst;       /* Number of instruction in window */
              uint64 specInst;   /* Number of speculative instructions */
              uint64 ldstInst;   /* Number of load/store instructions */
              uint64 ldstdepInst;/* Nubmer of instructions with LDST_DEP */
              uint64 regdepInst; /* Number of inst with REG_DEP* */
              uint64 squashInst; /* Number of squashed instructions */
          } iwin_hist[TOTAL_INST+1];
          struct {
             uint64 inst;        /* Number of inst in ldst buffer */
             uint64 doneInst;    /* Number of finished inst in ldst buffer */
             uint64 pendInst;    /* Number of pending inst */
             uint64 conflictInst; /* Number of conflicted inst */
             uint64 failedInst;  /* Number of failed inst. */
             uint64 stallInst;   /* Number of stalled inst. */
          } ldst_hist[LDST_BUFFER_SIZE+1]; 
          
        } sample_stats[NUM_MODES];

	int	icount;
	void	*mipsyPtr;
	};

extern	struct	s_cpu_state	cpu_state;

	/*
	 *  Status bit definitions for the various components of the model
	 */

#define	IWIN_BUSY	0x0001			/* Inst window: slot busy */
#define	IWIN_DEP2	0x0002			/* Dependency on reg 2	*/
#define	IWIN_DEP3	0x0004			/* Dependency on reg 3	*/
#define	IWIN_FLUSH	0x0008			/* Force instruction	*/
						/* window to empty out.	*/

#define	IWIN_AVAIL	0x0010			/* Ready to be executed	*/
#define	IWIN_LDST	0x0020			/* Is a load or store	*/
#define	IWIN_ISSUED	0x0040			/* Inst has been issued	*/
#define	IWIN_BRDLY	0x0080			/* Waiting for branch	*/
						/* delay to be fetched	*/

#define	IWIN_SPEC	0x0100			/* Speculative inst.	*/
#define	IWIN_SQUASH	0x0200			/* Squashed inst.	*/
#define	IWIN_STORE	0x0400			/* Is a store inst.	*/
#define	IWIN_CTL	0x0800			/* Dest is a special reg */

#define	IWIN_FAULT	0x1000			/* Instruction faulted	*/
#define	IWIN_LDST_DEP	0x2000			/* Load/store dependency */
#define	IWIN_ADDR_VALID	0x4000			/* Address field is valid */

					/* For precise interrupts:	*/
#define	IWIN_FREED	0x08000			/* Instruction can be freed */
#define	IWIN_DEFINE	0x10000			/* Instruction defines a reg */

#define	IWIN_BRANCH	0x20000			/* Branch instruction	*/
#define IWIN_UNCACHED	0x40000			/* Is an uncached load/store */
#define	IWIN_TLBFAULT	0x80000			/* Op suffered a TLB fault */
#define	IWIN_LDSTBUF	0x100000		/* In ldst_buffer	*/
#define	IWIN_ANNOTATED	0x200000		/* Invoke annotation at	*/
						/* graduation time	*/
#define IWIN_TAKENBR    0x400000                /* If branch, was taken. */

#define	BP_TAKEN	0x04			/* Branch prediction bits */
#define	BP_BOTH		0x02			/* Follow both threads?	*/
#define	BP_MAX_VAL	0x07			/* Clamp to this value	*/

#define	PredictTaken(pbits, likely)	\
		(((pbits) & BP_TAKEN) || ((likely) && ((pbits) >= BP_BOTH)))

#define	PRUNE_RIGHT	0x00			/* Which branch to prune? */
#define	PRUNE_LEFT	0x01

	/* Floating point condition code bit.	*/

#define	CONDBIT		0x00800000


	/*
	 *  PhaseA  -  Determine if the instruction is a load/store which
	 *		hasn't yet completed Phase A execution.  In a one
	 *		phase load operation, Phase A is always false.
	 */

#ifdef ONE_PHASE_LS

#define	PhaseA(inum)	0

#else

#define	PhaseA(inum)	\
	((st->iwin_flags [(inum)] & (IWIN_LDST|IWIN_ADDR_VALID)) == IWIN_LDST)

#endif



/************************************************************************/
/*									*/
/*		Macros for register access				*/
/*									*/
/************************************************************************/

	/* Fixed offsets to HI and LO registers	*/

#ifdef LITTLE_ENDIAN

#define	HIREG	(HILOREG+1)
#define	LOREG	HILOREG

#else

#define	HIREG	HILOREG
#define	LOREG	(HILOREG+1)

#endif

	/* Macros for coercing register types		*/

#define	Ireg(r1)	(st->regs[(r1)])
#define	Ureg(r1)	(((unsigned *)st->regs)[(r1)  ])
#define	Freg(r1)	(((float    *)st->regs)[(r1)  ])
#define	Dreg(r1)	(((double   *)st->regs)[(r1)/2])


/************************************************************************/
/*									*/
/*		Function Prototypes					*/
/*									*/
/************************************************************************/

extern	void (*optab[MAX_OP])(struct s_cpu_state *st, INST *ip, THREAD *th);

	/*
	 *  Procedures that implement the opcodes
	 */

extern void opILL(struct s_cpu_state *st, INST *ip, THREAD *th);
extern void opJ(struct s_cpu_state *st, INST *ip, THREAD *th);
extern void opJAL(struct s_cpu_state *st, INST *ip, THREAD *th);

extern void opBEQ(struct s_cpu_state *st, INST *ip, THREAD *th);
extern void opBNE(struct s_cpu_state *st, INST *ip, THREAD *th);
extern void opBLEZ(struct s_cpu_state *st, INST *ip, THREAD *th);
extern void opBGTZ(struct s_cpu_state *st, INST *ip, THREAD *th);
extern void opBLTZ(struct s_cpu_state *st, INST *ip, THREAD *th);
extern void opBGEZ(struct s_cpu_state *st, INST *ip, THREAD *th);
extern void opBLTZAL(struct s_cpu_state *st, INST *ip, THREAD *th);
extern void opBGEZAL(struct s_cpu_state *st, INST *ip, THREAD *th);