ms.h

一个用在mips体系结构中的操作系统

/*
 * Copyright (C) 1996-1998 by the Board of Trustees
 *    of Leland Stanford Junior University.
 * 
 * This file is part of the SimOS distribution. 
 * See LICENSE file for terms of the license. 
 *
 */


	/*
	 *  ms.h  -  Generic definitions for the MXS simulator component
	 *
	 *	Jim Bennett
	 *	1993, 1994, 1995
	 */

#ifdef MIPSY_MXS
#include <sys/types.h>
#include "annotations.h"
#if 0
#include "cpu_state.h"
#endif
#endif

#include <stdio.h>
#include "ms_param.h"
#include "ms_cache.h"
#include "ms_wrklst.h"
#include "mc_opc.h"

	/*
	 *  Global variables in the simulator
	 */

extern	int	true_inst_hi;		/* Instruction count (optional)	*/
extern	int	true_inst_lo;

extern	int	min_special_preg;	/* Range of special physical reg's */
extern	int	max_special_preg;

#define	preg_is_special(rg)	\
	(((rg) >= min_special_preg) && ((rg) <= max_special_preg))

extern	char	*statfilename;		/* File for MXS statistics	*/
#ifdef TRACE
extern	char	*tracefilename;
extern	FILE	*tracefile;		/* File for address trace	*/
extern	int	trace_writes;		/* If only writes should be traced */
#endif

#ifdef BREAKPOINT
extern	int	brkpt;			/* Global breakpoint register	*/
extern	int	jmpbrk;			/* Branch target breakpoint	*/
extern	int	cycbrk;			/* Cycle count breakpoint	*/
extern	int	linbrk;			/* Cache line breakpoint	*/
extern	int	membrk;			/* Memory breakpoint		*/
extern	int	opcbrk;			/* Opcode breakpoint		*/

extern	int	trace_reg;		/* Register for tracing		*/
extern	int	trace_preg;		/* Physical version of above	*/
#endif

#ifdef PRINT_INSTRUCTIONS
extern	int	enable_iprint;		/* Instruction print control	*/
extern	int	enable_fprint;		/* Branch processing print ctrl	*/
extern	int	enable_eprint;		/* Exception processing  "   "	*/
extern	int	iprint_frequency;	/* Sampling frequency for iprint */
#endif

	/*
	 *  Common parameters and fixed definitions.  Typically the
	 *	parameters are set large enough so that they don't cause
	 *	any slowdown.
	 */

#define	MAX_WORK_ITEMS	128		/* Size of worklist array	*/
#define	MAX_CALLBACK	 64		/* Number of memory system callbacks */

#define	MAX_FP		TOT_REG
#define	MIN_IVAR	MAX_FP
#define	MAX_VAR		MAX_FP

					/* Bound on physical registers	*/
#define	MAX_PREG	((TOT_REG + TOTAL_INST)*2)
					/* Pregs are allocated in pairs	*/

#define	SYSREG_L	2		/* Registers used by system calls */
#define	SYSREG_U	7

#ifdef MIPSY_MXS
#define	PC_INC	4
#else
#define	PC_INC	1
#endif



#ifndef MIPSY_MXS
extern	int	*symbuf;		/* Symbol table			*/
extern	int	symsize;

/************************************************************************/
/*									*/
/*	File header for the MXS executable (simulatable?) format	*/
/*									*/
/************************************************************************/

#define	MS_MAGIC	0x4d58534d

struct	ms_header
	{
	uint	magic;			/* Identify file type and	*/
	uint	version;		/* version of compiler		*/
	uint	revision;

	int	renamed;		/* Compiler options		*/
	int	scheduled;
	float	miss_probability;

	uint	data_base;		/* Location and length of data	*/
	uint	max_data;
	uint	text_base;		/* Location and length of text	*/
	uint	max_text;
	uint	start;
	uint	ct_size;		/* Compiled code segment	*/
	uint	sym_size;		/* Symbol table segment length	*/

	uint	hashsize;		/* Size of hash table		*/
	uint	hashprime;		/* Prime to access hash table	*/
	uint	entry_valid;		/* How many valid entries?	*/
	uint	entry_coll;		/* How many are collisions?	*/
	uint	collisions;		/* Number of overflow entries	*/
	uint	maxdepth;		/* Worst case collisions	*/
	uint	synonyms;		/* Number of address synonyms	*/
	};

struct	s_coll				/* Collision record from hash table */
	{
	uint	addr;
	uint	cadr;
	};

struct s_clnk				/* Linked list of collisions	*/
	{
	struct	s_clnk	*next;
	uint	addr;
	uint	cadr;
	};

struct s_sym				/* Symbol table entry		*/
	{
	uint	addr;
	int	height;
	int	cycle;
	int	len;
	};

#define	OUTSIDE_ADDR	((uint)0xffffffff)
#define	UNKNOWN_ADDR	((uint)0xfffffffe)
#define	COLLISION_ADDR	((uint)0xfffffffd)


	/*
	 *  Structure for mapping of text and data addresses
	 */

struct	s_procmap
	{
	uint	text_base;		/* Offset of text segment	*/
	uint	max_text;
	uint	data_base;		/* Offset of data segment	*/
	uint	data_top;		/* Top of data segment		*/

	char	*text_buf;		/* Pointers to segments		*/
	char	*data_buf;
	INST	*ctbuf;			/* Compiled code buffer		*/
	int	ctsize;

	uint	*bbhash;		/* Hash table for conversion	*/
	uint	*bbaddr;		/* of branch addresses to	*/
	struct s_clnk **bbcoll;		/* offsets into compiled code	*/

	uint	*adrhash;		/* And for branch addresses	*/
	struct s_clnk **adrcoll;	/* back to offsets		*/

	int	hashsize;		/* offsets into compiled code	*/
	int	hashprime;
	};

extern	struct	s_procmap	pmap;

#endif		/* !MIPSY_MXS	*/

/************************************************************************/
/*									*/
/*	Definitions for statistics gathering.				*/
/*									*/
/************************************************************************/


#define	ST_NO_EXCUSE		 0	/* Stalled for no reason	*/

	/* Fetch efficiency statistics	*/

#define	ST_FETCHES_TRIED	 1	/* Fetches attempted		*/
#define	ST_FETCHES		 2	/* Successful fetches		*/
#define ST_FETCH_EXPEND		 3	/* Failure  - Exception pending. */
#define	ST_FETCH_IW_FULL	 4	/* Failures - issue window full	*/
#define	ST_FETCH_RB_FULL	 5	/* Failures - reorder buf. full	*/
#define	ST_FETCH_THREAD		 6	/* Ran out of threads		*/
#define	ST_FETCH_NAME		 7	/* Rename failed, due to one of: */
#define	ST_REG_ERROR		 8	/* Reference to poisoned reg.	*/
#define	ST_REG_BUSY		 9	/* All registers in use		*/
#define	ST_REG_CLAIMED		10	/* Register preclaimed		*/
#define	ST_REG_SPEC		11	/* Special register still in use */

#define	ST_FETCH_STALL		20	/* Failures - threads stalled	*/
#define	ST_FETCH_STALLTHREAD	21	/* Fetch stall - not enough threads */
#define ST_FETCH_STALLBRANCH	22
#define ST_FETCH_STALLFPC	23
#define ST_FETCH_STALLICACHE	24
#define ST_FETCH_STALLITLB	25
#define ST_FETCH_STALLEXCEPT	26
#define	ST_FETCH_STALLSYS	27
#define	ST_FETCH_STALLCP0	28
#define	ST_FETCH_STALLSC	29

#define	ST_FETCH_STALL_OTH	30	/* Fetch stall - unidentified	*/
#define	ST_FETCH_STALL_INV	31	/* Fetch stall - invalid addr	*/
#define ST_FETCH_CACHEFAILURE   32

	/* Of the fetched instructions, what is their disposition?	*/

#define	ST_EXECUTED		40	/* Instructions executed	*/
#define	ST_EXBRANCH		41	/* Executed in branch unit	*/
#define	ST_PRUNED		42	/* Instructions squashed	*/
#define	ST_EXPRUNE		43	/* Executed, then squashed	*/

	/* Issue efficiency statistics	*/

#define	ST_ISSUE_STALLED	44	/* No issues this cycle		*/
#define	ST_EXCEPT		45	/* Interrupt stall cycles	*/
#define	ST_LSQ_FULL		46	/* Load/store queue is full	*/
#define	ST_SYSCALL		47	/* Force synchronization for syscall */
#define	ST_FPC			48	/* Force sync. for FP control write */

	/* Of the attempted issues, either they are executed	*/
	/* (ST_EXECUTED, above), or they are PhaseA issues,	*/
	/* or they fail, either due to an empty instruction	*/
	/* window, or to a stall waiting for results.		*/

#define	ST_ISSUE_TRIED		49	/* Count of issues attempted	*/
#define	ST_PHASE_A		50	/* Number of Phase A issues	*/
#define	ST_IWIN_EMPTY		51	/* No instructions available	*/
#define	ST_INST_STALLED		52	/* Instruction not ready	*/

	/* Reasons why instruction not ready	*/

#define	ST_IWIN_FLUSH		53	/* Waiting for IWIN to empty out */
#define	ST_LDST_DEP		54	/* Waiting on load/store dependency */
#define	ST_LDST_FULL		55	/* Couldn't reserve ldst buffer	*/
#define	ST_BR_DLY		56	/* Need to fetch opcode in branch delay	*/
#define	ST_SPEC_CTL		57	/* Speculative control write	*/
#define	ST_REG_DEP		58	/* Stalled on register dependency */

	/* Reasons for register dependencies	*/

#define	ST_NOT_ISSUED		60	/* Source inst not issued yet	*/
#define	ST_PC_DLY		61	/* Primary cache delay slot	*/
#define	ST_IMUL			62	/* Waiting for integer multiply	*/
#define	ST_IDIV			63	/* Waiting for integer divide	*/
#define	ST_FPADD		64	/* Waiting for FP add operation	*/
#define	ST_FPMUL		65	/* Waiting for FP multiply	*/
#define	ST_FPDIV		66	/* Waiting for FP divide	*/
#define	ST_FPSQRT		67	/* Waiting for FP square root	*/
#define	ST_FPCMP		68	/* Waiting for FP compare	*/
#define	ST_FPABS		69	/* Waiting for FP absolute value */
#define	ST_FPNEG		70	/* Waiting for FP negate	*/
#define	ST_FPCVT		71	/* Waiting for FP convert	*/
#define	ST_CACHE_LSQ		72	/* Waiting for load in queue	*/
#define	ST_CACHE_LBSY		73	/* Waiting in cache line busy q	*/
#define	ST_CACHE_BUS		74	/* Waiting for bus completion	*/

	/* Wasted or useless instructions	*/

#define	ST_NOP			75	/* No-op instruction		*/
#define	ST_BR_NOP		76	/* No-op in branch delay slot	*/

	/* Branch prediction statistics		*/

#define	ST_UNCOND_BR		80	/* Unconditional branch		*/
#define	ST_COND_BR		81	/* Number of conditional branches */
#define	ST_IND_BR		82	/* Number of indirect branches	*/

#define	ST_CORRECT_FALLTHRU	83	/* Correctly predicted branches	*/
#define	ST_CORRECT_W_FALLTHRU	84
#define	ST_CORRECT_W_TAKEN	85
#define	ST_CORRECT_TAKEN	86
#define	ST_CORRECT_IND_BR	87
#define ST_CORRECT_JRET		88
#define ST_CORRECT_LIKELY	89

#define	ST_INCORRECT_FALLTHRU	90	/* Incorrectly predicted branches */
#define	ST_INCORRECT_W_FALLTHRU	91
#define	ST_INCORRECT_TAKEN	92
#define	ST_INCORRECT_W_TAKEN	93
#define	ST_INCORRECT_IND_BR	94
#define ST_INCORRECT_JRET	95
#define ST_INCORRECT_LIKELY	96

	/* Memory subsystem statistics		*/

#define	ST_NLOADS		100	/* Total number of loads	*/
#define	ST_NSTORES		101	/* Total number of stores	*/
#define ST_LSOP_UNCACHED_LOAD	103
#define ST_LSOP_UNCACHED_STORE  104

	/* From standalone cache subsystem	*/

#define	ST_DREADMISS		105	/* Dirty read misses		*/
#define	ST_DWRITEMISS		106	/* Dirty write misses		*/
#define	ST_READMISS		107	/* Total read misses		*/
#define	ST_WRITEMISS		108	/* Total write misses		*/

	/* Load/store buffer statistics	*/

#define	ST_LDSTDEP_CONISSUE	110
#define ST_LDSTDEP		111
#define ST_LDSTDEP_FAIL		112
#define ST_LDSTDEP_CONFLICT	113

#define ST_LDST_RETIRE_LOAD	114
#define ST_LDST_RETIRE_STORE	115
#define ST_LDST_INVALIDLOAD	116
#define ST_LDST_WAIT		117
#define ST_LDST_RETIRE_SQUASH	118
#define ST_LDST_REFETCH		119
#define ST_LDST_BUF_SQUASH_ACT  120
#define ST_LDST_BUF_SQUASH	121

	/* Calls to ms_cache	*/

#define ST_CACHE		130
#define ST_CACHE_SQUASHED	131
#define ST_CACHE_CONFLICT	132
#define ST_CACHE_LOAD		133
#define ST_CACHE_STORE		134
#define ST_CACHE_HIT		135
#define ST_CACHE_MISS		136
#define ST_CACHE_FAILURE	137
#define ST_CACHE_LOADHIT	138
#define ST_CACHE_SCFAILURE	139


#define	ST_VCYCS		140	/* Number of cycles in valid	*/
					/* (renameable) procedures.	*/
#define ST_RUN_CYCLES		141	/* Number of calls to ms_cycle_once */
					/* (for Mipsy version).		*/

	/* Exception handling statistics	*/

#define ST_EXCEPT_INST		151
#define ST_EXCEPT_LDST		152
#define ST_EXCEPT_SQUASH	153

#define ST_EXCEPT_WAIT		154	/* Waiting with except pending	*/
#define ST_EXCEPT_ITLB		155
#define ST_EXCEPT_INTR		156
#define ST_EXCEPT_TAKEN		157
#define ST_EXCEPT_COHERENCY	158
#define ST_EXCEPT_SWITCH	159
#define ST_EXCEPT_SWITCH_INST	160
#define ST_EXCEPT_COHER_INST	161
#define ST_EXCEPT_COHER_LDST	162
#define ST_EXCEPT_COHER_SQUASH  163

	/* Graduation statistics	*/

#define ST_GRAD_PHASEASTALL     166
#define ST_GRAD_ISSUESTALL      167
#define ST_GRAD_ICACHESTALL     168
#define ST_GRAD_FLUSHSTALL      169
#define ST_GRADS_TRIED		170
#define ST_GRAD_EXPEND		171
#define ST_GRAD_LDSTALL		172
#define ST_GRAD_SQUASHED	173
#define ST_GRAD_SQUASHED_LDST	174
#define ST_GRAD_INST		175
#define ST_GRAD_INST_LDST	176
#define ST_GRAD_STSTALL         177
#define ST_GRAD_EMPTYSTALL      178
#define ST_GRAD_MISCSTALL       179

#define	ST_NTYPES		180	/* Number of stall types	*/


	/*
	 *  Macro for incrementing a statistics counter
	 */

#define	TICK_COUNT	100000		/* Number of cycles per tick mark */
#define	TICK_DIGITS	5		/* Digits in tick count		*/

#ifdef MIPSY_MXS
#define SIM_MEMORY(x) ((x))
#define CPUNUM(_st) (((CPUState *)((_st)->mipsyPtr))->myNum)
#define bp_pc_to_index(_pc) (((_pc)>>2)&(BP_TABLE_SIZE-1))
#define _smode(_st) CURRENT_MODE((((CPUState *)(_st)->mipsyPtr)))

/* SAH - Warning -> this used to use modes. */
#define	IncStat(sttype)	 st->stats[0][(sttype)]++;


#define	AddToStat(sttype,cnt)	st->stats[_smode(st)][(sttype)] += (cnt);    

#else /* MIPSY_MXS */

#define	NUM_MODES	1

#define	IncStat(sttype)							\
	{ st->stats[0].stat_cycles[(sttype)]++;				\
	  if (st->stats[0].stat_cycles[(sttype)] >= TICK_COUNT)		\
		{ st->stats[0].stat_cycles[(sttype)] -= TICK_COUNT;	\
		st->stats[0].stat_ticks[(sttype)]++; } }