📄 decoder.h
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/* * Copyright (C) 1996-1998 by the Board of Trustees * of Leland Stanford Junior University. * * This file is part of the SimOS distribution. * See LICENSE file for terms of the license. * */#ifndef DECODER_H#define DECODER_H/* Opcode information not in that file */#define bcfl_op 0x02#define bctl_op 0x03/* Simos hacked opcodes */#define SIMOS_HACKED_SYSCALL 0x8c020003 /* lw v0, 3($0) */#define SIMOS_HACKED_TNS 0x8c880001 /* lw t0, 1(a0) *//* This is a reserved opcode in R10000 */#define mendel_tns (swc2_op+1)/* maximum number of instructions in one group */extern int maxInGroup;typedef unsigned Instruction;/* Register allocation information */typedef struct { int reg_num; int num_src; int alloc_reg;}alloc_reg_t;/* Absolute max number of instructions in a basic block. Anything *//* over 50 seems reasonable */#define INST_GRP_LIMIT 60typedef struct { int cpuNum; VA virt_pc; PA phys_pc; MA maPC; int GrpLen; PA next_phys_pc; MA next_maPC; int numDMemoryAcesses; int numIMemoryAcesses; int isKseg0; /* This flag tells us to not chain this block (can't chain from */ /* kernel to user) */ int is_rfe_block; /* This flag tells us to skip register allocation */ int no_reg_allocate; /* This flag tells us if the delay slot squashes a regsiter that is */ /* used by the control transfer instruction */ int is_delay_slot_instr; int delay_slot_reg_conflict; alloc_reg_t* reg2alloc; Instruction instrs[INST_GRP_LIMIT]; int pcAnn[INST_GRP_LIMIT]; /* Reg allocation information structures, referenced by register number */}InstrGrp; /***************************************************************** * This information comes from "MIPS RISC ARCHITECTURE" and is * * found on page 3-1. * * * * All instructions are 32 bits and aligned on a word boundary. * *****************************************************************//* Macros to EXTRACT each instruction field. The lowest order bit will be at position 0 */#define MAJOR_OPCODE(_instr) ( ((unsigned)_instr >> 26 ) & 0x3f )#define rs(_inst) (((unsigned)_inst >> 21) & 0x1f )#define rt(_inst) (((unsigned)_inst >> 16) & 0x1f )#define rd(_inst) (((unsigned)_inst >> 11) & 0x1f )#define SHAMT(_inst) (((unsigned)_inst >> 6) & 0x1f )#define fs(_inst) (((unsigned)_inst >> 11) & 0x1f )#define ft(_inst) (((unsigned)_inst >> 16) & 0x1f )#define fd(_inst) (((unsigned)_inst >> 6) & 0x1f )#define FUNC(_inst) ((unsigned)_inst & 0x0000003f )#define FORMAT(_inst) (((uint)_inst >> 21) & 0x1f )/* Doing it this way allows the values to be sign extended */#define IMMED(_inst) ( ((int)_inst << 16 ) >> 16 )#define TARGET(_inst) ((unsigned)_inst & 0x03ffffff )#define IS_FCMP(_inst) (((unsigned)_inst >> 3) & 0x3 )#define IS_CP0_FUNC(_inst) (((unsigned)_inst >> 25 ) & 0x1 )/* NOTE: this does not match the format in the MIPS book, but the kernel *//* and debugger agree, so that's what we will use */#define BREAK_CODE(_inst) (((unsigned)_inst >> 16 ) & 0x3ff )extern void DecoderInit( void );extern void DecodeInstrs( InstrGrp*,int cpuNum, VA pc, int is_delay_slot_instr );extern int IsCtlInstr(uint inst);extern VA EndOfBB(VA pc, MA mA);/* XXX BL: added in this floating point stuff; should probably be in mips_arch.h */#define FCMP_BITS (6<<3)#define FC_BIT (1<<23) /* fcr 31 condition code bit */#define FBC_BIT (1<<16) /* compare sense of FP branch */#define F_FMT(x) (((x)>>21)&15) /* technically 31, but 15 for mips_arch.h *//* decode floating point compare condition field */#define FL_BIT (1<<2) /* cond:2 = less than */#define FEQ_BIT (1<<1) /* cond:1 = equal */#define FUN_BIT (1<<0) /* cond:0 = unordered *//* MIPS data formats: * floats: * sign:1 | exponent:8 | fraction:23 * * doubles: * sign:1 | exponent:11 | fraction:52 */#define FFEMAX (127) /* max exponent for floats */#define FDEMAX (1023) /* max exponent for doubles */#endif /* DECODE_H */
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