mips_arch.h

一个用在mips体系结构中的操作系统

#define SR_KSU_KS	0x00000008	/* 0-->kernel 1-->supervisor */
#define SR_KSU_SUP	SR_KSU_KS
#define SR_ERL		0x00000004	/* Error level, 1=>cache error */
#define SR_EXL		0x00000002	/* Exception level, 1=>exception */
#define SR_IE		0x00000001	/* interrupt enable, 1=>enable */
#define SR_IEC		SR_IE		/* compat with R3000 source */
#define SR_PREVMODE	SR_KSU_MSK	/* previous kernel/user mode */
#define SR_ZEROS        (3<<23)
/*
 * Cause Register
 */
#define	CAUSE_BD	0x80000000	/* Branch delay slot */
#define	CAUSE_CEMASK	0x30000000	/* coprocessor error */
#define	CAUSE_CESHIFT	28

/* Interrupt pending bits */
#define	CAUSE_IP8	0x00008000	/* Internal level 8 pending */
#define	CAUSE_IP7	0x00004000	/* External level 7 pending */
#define	CAUSE_IP6	0x00002000	/* External level 6 pending */
#define	CAUSE_IP5	0x00001000	/* External level 5 pending */
#define	CAUSE_IP4	0x00000800	/* External level 4 pending */
#define	CAUSE_IP3	0x00000400	/* External level 3 pending */
#define	CAUSE_SW2	0x00000200	/* Software level 2 pending */
#define	CAUSE_SW1	0x00000100	/* Software level 1 pending */

               /* Cause bits set by external interrupts */
#define CAUSE_EXTINTBITS   (CAUSE_IP7|CAUSE_IP6|CAUSE_IP5|CAUSE_IP4|CAUSE_IP3)

#define	CAUSE_IPMASK	0x0000FF00	/* Pending interrupt mask */
#define	CAUSE_IPSHIFT	8
#define	CAUSE_EXCMASK	0x0000007C	/* Cause code bits */

#define	CAUSE_EXCSHIFT	2

#define CAUSE_ZEROS     ((0x1<<30)|(0xfff<<16)|(1<<7)|0x3)

/* Cause register exception codes */
#define	EXC_CODE(x)	((x)<<2)

/* Hardware exception codes */
#define	EXC_INT		EXC_CODE(0)	/* interrupt */
#define	EXC_MOD		EXC_CODE(1)	/* TLB mod */
#define	EXC_RMISS	EXC_CODE(2)	/* Read TLB Miss */
#define	EXC_WMISS	EXC_CODE(3)	/* Write TLB Miss */
#define	EXC_RADE	EXC_CODE(4)	/* Read Address Error */
#define	EXC_WADE	EXC_CODE(5)	/* Write Address Error */
#define	EXC_IBE		EXC_CODE(6)	/* Instruction Bus Error */
#define	EXC_DBE		EXC_CODE(7)	/* Data Bus Error */
#define	EXC_SYSCALL	EXC_CODE(8)	/* SYSCALL */
#define	EXC_BREAK	EXC_CODE(9)	/* BREAKpoint */
#define	EXC_II		EXC_CODE(10)	/* Illegal Instruction */
#define	EXC_CPU		EXC_CODE(11)	/* CoProcessor Unusable */
#define	EXC_OV		EXC_CODE(12)	/* OVerflow */
#define EXC_TRAP	EXC_CODE(13)	/* Trap exception */
#define EXC_VCEI	EXC_CODE(14)	/* Virt. Coherency on Inst. fetch */
#define EXC_FPE	        EXC_CODE(15)	/* Floating Point Exception */
#define EXC_WATCH	EXC_CODE(23)	/* Watchpoint reference */
#define EXC_VCED	EXC_CODE(31)	/* Virt. Coherency on data read */

/* Write masks for CP0 registers. */
#ifndef _LANGUAGE_ASSEMBLY
typedef struct {
    int size;  /* 0 = 32bit, 1 = 64bit, -1 = notvalid */
    uint64 zero_mask;    /* bits must be zero */
    int read_only;                   /* non zer0 if read-only */
} Cp0RegControl;

#endif

#define CP0_REG_CONTROL_ARRAY { \
    {0, TLBINX_ZEROS, 0x0},            /* 0 - 32bit Index */   \
    {0, TLBRAND_RANDMASK, -1},         /* 1 - 32bit Random */  \
    {1, TLBLO_ZEROS, 0x0},             /* 2 - 64bit TLBLo0 */    \
    {1, TLBLO_ZEROS, 0x0},             /* 3 - 64bit TLBLo1 */    \
    {1, TLBCTXT_ZEROS, 0x0},           /* 4 - 64bit Context */   \
    {0, TLBPGMASK_ZEROS,0x0},          /* 5 - 32bit PageMask */  \
    {0, TLBWIRED_ZEROS,0x0},           /* 6 - 32bit wired */     \
    {-1,-1LL,0},                       /* 7 - notvalid */        \
    {1, 0x0,-1},                       /* 8 - 64bit badVaddr */  \
    {0, 0x0,0},                        /* 9 - 32bit count */     \
    {1,TLBHI_ZEROS, 0},                /* 10 - 64bit TLBHI */    \
    {0, 0x0,0},                        /* 11 - 32bit compare */  \
    {0, SR_ZEROS,0},                   /* 12 - 32bit status */   \
    {0, CAUSE_ZEROS,0},                /* 13 - 32bit cause */    \
    {1, 0,0},                          /* 14 - 64bit EPC */      \
    {0, C0_PRID_ZEROS, -1},            /* 15 - 32bit PRid reg */ \
    {0, 0, -1},                        /* 16 - 32bit config reg */  \
    {0, 0, 0},                         /* 17 - 32bit LL reg */   \
    {0, 0, 0},                         /* 18 - 32bit watchLo */  \
    {0, 0xffffff00, 0},                /* 19 - 32bit watchHi */  \
    {1, 0xfLL, 0},                     /* 20 - 64bit xcontext */ \
    {0, 0xffff0000, 0},                /* 21 - 32bit framemask */ \
    {1, 0, -1},                        /* 22 - 64bit diag reg. */ \
    {-1, -1LL, 0},                     /* 23 - notvalid */        \
    {-1, -1LL, 0},                     /* 24 - notvalid */        \
    {0, 0xfffffe00, 0},                /* 25 - 32bit perf counter */ \
    {0, 0xfffffc00, 0},                /* 26 - 32bit ECC reg */    \
    {0, 0,0} ,                         /* 27 32bit cache reg */    \
    {0, 0,0} ,                         /* 28 32bit cache reg */    \
    {0, 0,0} ,                         /* 29 32bit cache reg */    \
    {1,0,0},                           /* 30, 64bit ErrorPC */     \
    {-1,0,0}}                          /* 31 -  not valid */      


/*
 * XXX I think that TORNADO is correct on this one
 * XXX should check that it is ok with IRIX and 
 * XXX remove the ifdef. bugnion
 */
#if defined(TORNADO) || defined(IRIX6_4)
#define COUNTER_FREQUENCY_DIVIDER 2
#else
#define COUNTER_FREQUENCY_DIVIDER 1
#endif



/* Instruction op codes */
/* major opcodes */
#define spec_op		0x00
#define bcond_op	0x01
#define j_op		0x02
#define jal_op		0x03

#define beq_op		0x04
#define bne_op		0x05
#define blez_op		0x06
#define bgtz_op		0x07

#define addi_op		0x08
#define addiu_op	0x09
#define slti_op		0x0A
#define sltiu_op	0x0B

#define andi_op		0x0C
#define ori_op		0x0D
#define xori_op		0x0E
#define lui_op		0x0F

#define cop0_op		0x10
#define cop1_op		0x11
#define cop2_op		0x12
#define cop1x_op        0x13

#define beql_op		0x14
#define bnel_op		0x15
#define blezl_op	0x16
#define bgtzl_op	0x17

#define daddi_op        0x18
#define daddiu_op       0x19
#define ldl_op          0x1A
#define ldr_op          0x1B

#define lb_op		0x20
#define lh_op		0x21
#define lwl_op		0x22
#define lw_op		0x23

#define lbu_op		0x24
#define lhu_op		0x25
#define lwr_op		0x26
#define lwu_op		0x27

#define sb_op		0x28
#define sh_op		0x29
#define swl_op		0x2A
#define sw_op		0x2B

#define sdl_op		0x2C
#define sdr_op		0x2D
#define swr_op		0x2E
#define cache_op	0x2F

#define ll_op		0x30
#define lwc1_op		0x31
#define lwc2_op		0x32
#define pref_op		0x33

#define lld_op		0x34
#define ldc1_op		0x35
#define ldc2_op		0x36
#define	ld_op		0x37

#define sc_op		0x38
#define swc1_op		0x39
#define swc2_op		0x3A

#define scd_op		0x3C
#define sdc1_op		0x3D
#define sdc2_op		0x3E
#define	sd_op		0x3F

/* func field of spec opcode */
#define sll_op		0x00
#define movc_op         0x01
#define srl_op		0x02
#define sra_op		0x03

#define sllv_op		0x04
#define srlv_op		0x06
#define srav_op		0x07

#define jr_op		0x08
#define jalr_op		0x09
#define movz_op         0x0A
#define movn_op         0x0B

#define syscall_op	0x0C
#define break_op	0x0D
#define spim_op		0x0E
#define sync_op		0x0F

#define mfhi_op		0x10
#define mthi_op		0x11
#define mflo_op		0x12
#define mtlo_op		0x13

#define dsllv_op	0x14
#define dsrlv_op	0x16
#define dsrav_op	0x17

#define mult_op		0x18
#define multu_op	0x19
#define div_op		0x1A
#define divu_op		0x1B

#define dmult_op	0x1C
#define dmultu_op	0x1D
#define ddiv_op		0x1E
#define ddivu_op	0x1F

#define add_op		0x20
#define addu_op		0x21
#define sub_op		0x22
#define subu_op		0x23

#define and_op		0x24
#define or_op		0x25
#define xor_op		0x26
#define nor_op		0x27

#define slt_op		0x2A
#define sltu_op		0x2B

#define dadd_op		0x2C
#define daddu_op	0x2D
#define dsub_op		0x2E
#define dsubu_op	0x2F

#define tge_op		0x30
#define tgeu_op		0x31
#define tlt_op		0x32
#define tltu_op		0x33

#define teq_op		0x34
#define tne_op		0x36

#define dsll_op         0x38
#define dsrl_op         0x3A
#define dsra_op         0x3B

#define dsll32_op       0x3C
#define dsrl32_op       0x3E
#define dsra32_op       0x3F

/* rt field of bcond opcodes */
#define bltz_op		0x00
#define bgez_op		0x01
#define bltzl_op	0x02
#define bgezl_op	0x03

#define spimi_op	0x04

#define tgei_op		0x08
#define tgeiu_op	0x09
#define tlti_op		0x0A
#define tltiu_op	0x0B

#define teqi_op		0x0C
#define tnei_op		0x0E

#define bltzal_op	0x10
#define bgezal_op	0x11
#define bltzall_op	0x12
#define bgezall_op	0x13

/* rs field of cop opcodes */
#define mfc_op		0x00
#define dmfc_op		0x01
#define cfc_op		0x02
#define mtc_op		0x04
#define dmtc_op		0x05
#define ctc_op		0x06
#define bc_op		0x08
#define cop_op		0x10
#define copd_op		0x11
#define copw_op		0x14
#define copl_op		0x15
#define copm_op         0x18

/* func field of cop0 COI opcodes */
#define tlbr_op		0x01
#define tlbwi_op	0x02
#define tlbwr_op	0x06
#define tlbp_op		0x08
#define rfe_op		0x10
#define eret_op		0x18

/* func field of cop0 COM opcodes */
#define tlbr1_op	0x01
#define tlbw_op         0x02
#define tlbp1_op	0x08
#define dctr_op         0x09
#define dctw_op         0x0A

/* fmt field of cop1 opcodes */
#define	s_fmt		0
#define	d_fmt		1
#define	e_fmt		2
#define q_fmt		3
#define	w_fmt		4
#define l_fmt		5

/* func field of cop1/{s,d,w} opcodes */
#define fadd_op		0x00
#define fsub_op		0x01
#define fmul_op		0x02
#define fdiv_op		0x03

#define fsqrt_op	0x04
#define fabs_op		0x05
#define fmov_op		0x06
#define fneg_op		0x07

#define froundl_op	0x08
#define ftruncl_op	0x09
#define fceill_op	0x0a
#define ffloorl_op	0x0b

#define fround_op	0x0c
#define ftrunc_op	0x0d
#define fceil_op	0x0e
#define ffloor_op	0x0f

#define fmovc_op        0x11
#define fmovz_op        0x12
#define fmovn_op        0x13

#define frecip_op       0x15
#define frsqrt_op       0x16

#define fcvts_op	0x20
#define fcvtd_op	0x21
#define fcvte_op	0x22

#define fcvtw_op	0x24
#define fcvtl_op	0x25

#define fcmp_op		0x30

/* func field of cop1x opcodes */

#define lwxc1_op        0x00
#define ldxc1_op        0x01
#define pfetch_op       0x07
#define swxc1_op        0x08
#define sdxc1_op        0x09
#define madd_s_op       0x20
#define madd_d_op       0x21
#define madd_e_op       0x22
#define msub_s_op       0x28
#define msub_d_op       0x29
#define msub_e_op       0x2a
#define nmadd_s_op      0x30
#define nmadd_d_op      0x31
#define nmadd_e_op      0x32
#define nmsub_s_op      0x38
#define nmsub_d_op      0x39
#define nmsub_e_op      0x3a

/* func field for mad opcodes (ma_format.func) */
#define madd_op         0x08
#define msub_op         0x0a
#define nmadd_op        0x0c
#define nmsub_op        0x0e

#endif /* MIPS_ARCH_H */