mips_arch.h

一个用在mips体系结构中的操作系统

#define REG_NPC    33
#define REG_HI     34
#define REG_LO     35

#define REG_NONE   48

#define REG_TA0    REG_T4
#define REG_TA1    REG_T5
#define REG_TA2    REG_T6
#define REG_TA3    REG_T7

/* A regdef.h style register naming convention */
/* Zero Register */
#define G0 0

/* Assembler Register */
#define ATR 1

/* used for interger return and static link */
#define V0 2
#define V1 3

/* Argument Registers */
#define A0 4
#define A1 5
#define A2 6
#define A3 7

/* Temporary Registers */
#define T0 8
#define T1 9
#define T2 10
#define T3 11
#define T4 12 
#define T5 13
#define T6 14
#define T7 15

/* Saved Registers */
#define S0 16
#define S1 17
#define S2 18
#define S3 19
#define S4 20
#define S5 21
#define S6 22
#define S7 23

#define T8 24
#define T9 25

#define K0 26
#define K1 27
#define GP 28

#define SP 29	

#define S8 30
#define FP 30

#define RA 31


/* Cop 0 SR */
#define assC0_SR 12

/* Floating Point Coprocessor (1) registers */
/* Each FPR is the concatenation of two FGR's */

#define REG_FPR_0   BASE_FPR_OFFSET+0
#define REG_FPR_2   BASE_FPR_OFFSET+8
#define REG_FPR_4   BASE_FPR_OFFSET+16
#define REG_FPR_6   BASE_FPR_OFFSET+24
#define REG_FPR_8   BASE_FPR_OFFSET+32
#define REG_FPR_10  BASE_FPR_OFFSET+40
#define REG_FPR_12  BASE_FPR_OFFSET+48
#define REG_FPR_14  BASE_FPR_OFFSET+56
#define REG_FPR_16  BASE_FPR_OFFSET+64
#define REG_FPR_18  BASE_FPR_OFFSET+72
#define REG_FPR_20  BASE_FPR_OFFSET+80
#define REG_FPR_22  BASE_FPR_OFFSET+88
#define REG_FPR_24  BASE_FPR_OFFSET+96
#define REG_FPR_26  BASE_FPR_OFFSET+104
#define REG_FPR_28  BASE_FPR_OFFSET+112
#define REG_FPR_30  BASE_FPR_OFFSET+120

/****************************************/
/* FCR31 is the Control/Status Register */
/* FS bit         [24]                  */
/* Condition bit  [23]                  */
/* Cause          [17:12]               */
/* Enables        [11:7]                */
/* Flags          [6:2]                 */
/* Rounding Mode  [1:0]                 */
/*           (Page 7-6)                 */
/****************************************/

#define ROUND_TO_NEAREST	0
#define ROUND_TO_ZERO		1
#define ROUND_TO_PLUS_INFINITY	2
#define ROUND_TO_MINUS_INFINITY	3

#define FPCSR_FLUSH_ZERO	0x01000000
#define	FPCSR_UNIMP		0x00020000
#define	FPCSR_EXCEPTIONS	0x0003f000	/* all exceptions */
#define	FPCSR_ENABLES		0x00000f80
#define	FPCSR_FLAGS		0x0000007c

/************************************************/
/* FCR0 is the Implementation/Revision Register */
/* Implementation Number [15:8]                 */
/* Revision Number       [7:0]                  */
/*               (Page 7-11)                    */
/************************************************/

#define S_csr_c  23
#define M_csr_c  (1<<S_csr_c)

/*
 * Coprocessor 0 registers
 * Some of these are r4000 specific.
 */
#ifdef _LANGUAGE_ASSEMBLY
#define	C0_INX		$0
#define	C0_RAND		$1
#define	C0_TLBLO_0	$2
#define	C0_TLBLO_1	$3
#define	C0_CTXT		$4
#define	C0_PGMASK	$5		/* page mask */
#define	C0_TLBWIRED	$6		/* # wired entries in tlb */
   /* 7 is not used */
#define	C0_BADVADDR	$8
#define	C0_COUNT	$9		/* free-running counter */
#define	C0_TLBHI	$10
#define	C0_COMPARE	$11		/* counter comparison reg. */
#define	C0_SR		$12
#define	C0_CAUSE	$13
#define	C0_EPC		$14
#define	C0_PRID		$15		/* revision identifier */
#define	C0_CONFIG	$16		/* hardware configuration */
#define	C0_LLADDR	$17		/* load linked address */
#define	C0_WATCHLO	$18		/* watchpoint */
#define	C0_WATCHHI	$19		/* watchpoint */
#define C0_XCTXT        $20 
#define C0_FRAMEMASK    $21
#define C0_BRDIAG       $22
  /* 23 & 24 are not defined */
#define C0_PC           $25
#define	C0_ECC		$26		/* S-cache ECC and primary parity */
#define	C0_CACHE_ERR	$27		/* cache error status */
#define	C0_TAGLO	$28		/* cache operations */
#define	C0_TAGHI	$29		/* cache operations */
#define	C0_ERROR_EPC	$30		/* ECC error prg. counter */


# else	/* ! _LANGUAGE_ASSEMBLY */

#define	C0_INX		0
#define	C0_RAND		1
#define	C0_TLBLO_0	2
#define	C0_TLBLO_1	3
#define	C0_CTXT		4
#define	C0_PGMASK	5		/* page mask */
#define	C0_TLBWIRED	6		/* # wired entries in tlb */
   /* 7 is not used */
#define	C0_BADVADDR	8
#define	C0_COUNT	9		/* free-running counter */
#define	C0_TLBHI	10
#define	C0_COMPARE	11		/* counter comparison reg. */
#define	C0_SR		12
#define	C0_CAUSE	13
#define	C0_EPC		14
#define	C0_PRID		15		/* revision identifier */
#define	C0_CONFIG	16		/* hardware configuration */
#define	C0_LLADDR	17		/* load linked address */
#define	C0_WATCHLO	18		/* watchpoint */
#define	C0_WATCHHI	19		/* watchpoint */
#define C0_XCTXT        20 
#define C0_FRAMEMASK    21
#define C0_BRDIAG       22
  /* 23 & 24 are not defined */
#define C0_PC           25
#define	C0_ECC		26		/* S-cache ECC and primary parity */
#define	C0_CACHE_ERR	27		/* cache error status */
#define	C0_TAGLO	28		/* cache operations */
#define	C0_TAGHI	29		/* cache operations */
#define	C0_ERROR_EPC	30		/* ECC error prg. counter */

   /* C0_PRID values */
#define C0_IMPMASK      0xff00
#define C0_IMPSHIFT     8
#define C0_REVMASK      0xff
#define C0_MAJREVMASK   0xf0
#define C0_MAJREVSHIFT  4
#define C0_MINREVMASK   0xf
#define C0_PRID_ZEROS   0xffff0000

/* Target cache */
#define	CACH_PI		0x0	/* specifies primary inst. cache */
#define	CACH_PD		0x1	/* primary data cache */
#define	CACH_SI		0x2	/* secondary instruction cache */
#define	CACH_SD		0x3	/* secondary data cache */

/* Cache operations */
#define	C_IINV		0x0	/* index invalidate (inst, 2nd inst) */
#define	C_IWBINV	0x0	/* index writeback inval (d, sd) */
#define	C_ILT		0x4	/* index load tag (all) */
#define	C_IST		0x8	/* index store tag (all) */
#define	C_CDX		0xc	/* create dirty exclusive (d, sd) */
#define	C_HINV		0x10	/* hit invalidate (all) */
#define	C_HWBINV	0x14	/* hit writeback inv. (d, sd) */
#define	C_FILL		0x14	/* fill (i) */
#define C_BARRIER       0x14    /* cache barrier (i) R10000 */
#define	C_HWB		0x18	/* hit writeback (i, d, sd) */
#define	C_HSV		0x1c	/* hit set virt. (si, sd) */


#endif	/* _LANGUAGE_ASSEMBLY */


/*
 * TLB size constants
 */


#define NTLBENTRIES_R4000   48
#define NTLBENTRIES_R10000  64
#define MAX_NTLBENTRIES	64    /* Maximum size of TLB */

#define VA_VALID_BITS       44
#define PA_VALID_BITS       40

#ifdef oldR40000
#define VA_VALID_BITS       40
#define PA_VALID_BITS       36
#endif



#if defined(SIM_MIPS32)

#define TLBHI_VPN2MASK	     0xffffe000
#define TLBHI_FILLMASK       0xffffffff
#define TLBHI_REGIONMASK     0x80000000
#define TLBHI_REGIONSHIFT    31

#else


#define TLBHI_VPN2MASK     0xfffffffe000LL	/* 44bits on R10000 */
#define TLBHI_FILLMASK       0xc0000fffffffffffLL

#ifdef oldR4000
#define TLBHI_VPN2MASK      0xffffffe000LL	/* 40 bit virtual
                                                   address on r4000 */
#define TLBHI_FILLMASK       0xc00000ffffffffffLL
#endif

#define TLBHI_REGIONMASK    0xc000000000000000LL
#define TLBHI_REGIONSHIFT       62

#endif

#define TLBHI_VPN2SHIFT         13
#define TLBHI_PIDMASK		0xff
#define TLBHI_PIDSHIFT	        0
#define TLBHI_ZEROS            (0x1f<<8)


#define TLBHI_NPID		255		/* 255 to fit in 8 bits */
#define TLBHI_G                0x00001000      /* G bit in tlb hi */
#define STATIC_VPN2SHIFT       13              

#if defined(SIM_MIPS32)
#define TLBLO_PFNMASK		0x3fffffc0
#define TLBLO_UNCACHED_ATTR     0x0
#else

#define TLBLO_PFNMASK	       0x3ffffffc0LL     
#define TLBLO_UNCACHED_ATTR    0xc000000000000000LL
#ifdef oldR4000
#define TLBLO_PFNMASK	       0x3fffffc0
#define TLBLO_UNCACHED_ATTR    0x0LL
#endif
#endif

#define TLBLO_PFNSHIFT		6
#define TLBLO_CACHMASK		0x38		/* cache coherency algorithm */
#define TLBLO_CACHSHIFT	        3

#define CBIT_UNCACHED           2
#define CBIT_NONCOHERENT        3
#define CBIT_EXCLUSIVE          4
#define CBIT_EXCLUSIVE_WRITE    5
#define CBIT_UPDATE             6
#define CBIT_UNCACHED_ACCEL     7

#define TLBLO_UNCACHED	       (CBIT_UNCACHED<<TLBLO_CACHSHIFT)		/* not cached */
#define TLBLO_COHRNT_EXL       (CBIT_EXCLUSIVE<<TLBLO_CACHSHIFT)      /* coherent exclusive */
#define TLBLO_COHRNT_UPDTW     (CBIT_UPDATE<<TLBLO_CACHSHIFT)        /* coherent update on write */ 
#define TLBLO_EXLWR	       (CBIT_EXCLUSIVE_WRITE<<TLBLO_CACHSHIFT)	/* Exclusive write */
#define TLBLO_UNCACHED_ACCEL  (CBIT_UNCACHED_ACCEL<<TLBLO_CACHSHIFT)		/* not cached */

#define TLBLO_D		0x4		/* writeable */
#define TLBLO_V		0x2		/* valid bit */
#define TLBLO_G		0x1		/* global access bit */

#define TLBLO_ZEROS     ~(TLBLO_PFNMASK|TLBLO_G|TLBLO_V|TLBLO_D|TLBLO_CACHMASK|TLBLO_UNCACHED_ATTR)

#define TLBINX_INXMASK		0x3f
#define TLBINX_INXSHIFT	        0
#define TLBINX_ZEROS            0x7fffffc0

#define TLBRAND_RANDMASK	0x3f
#define TLBRAND_RANDSHIFT	0
#define TLBRAND_ZEROS           ~TLBRAND_RANDMASK

#define TLBWIRED_WIREDMASK	0x3f
#define TLBWIRED_ZEROS          ~TLBWIRED_WIREDMASK


#define TLBCTXT_VPNSHIFT	4
#define TLBCTXT_VPNMASK         0x7ffff0
#define TLBCTXT_BASESHIFT	23
#define TLBCTXT_ZEROS           0xf

#define TLBCTXT32_BASEMASK	0xff800000
#define TLBCTXT32_BASEBITS	9
#define TLBCTXT64_BASEMASK	0xffffffffff800000LL
#define TLBCTXT64_BASEBITS	41


#define TLBPGMASK_4K		(0x0 << 13)
#define TLBPGMASK_16K		(0x3 << 13)
#define TLBPGMASK_64K		(0xf << 13)
#define TLBPGMASK_256K		(0x3f << 13)
#define TLBPGMASK_1M		(0xff << 13)
#define TLBPGMASK_4M		(0x3ff << 13)
#define TLBPGMASK_16M		(0xfff << 13)
#define TLBPGMASK_NUMSIZES       7
#define TLBPGMASK_ZEROS         0xfe001fff

#define TLBFRAMESHIFT           18


#define CNFIG_IC_SHIFT          29  
#define CNFIG_DC_SHIFT          26
#define CNFIG_SS_SHIFT          16

/*
 * Interrupt enable bits
 * (NOTE: bits set to 1 enable the corresponding level interrupt)
 */
#define SR_IMASK	0x0000ff00	/* Interrupt mask */
#define SR_IMASK8	0x00000000	/* mask level 8 */
#define SR_IMASK7	0x00008000	/* mask level 7 */
#define SR_IMASK6	0x0000c000	/* mask level 6 */
#define SR_IMASK5	0x0000e000	/* mask level 5 */
#define SR_IMASK4	0x0000f000	/* mask level 4 */
#define SR_IMASK3	0x0000f800	/* mask level 3 */
#define SR_IMASK2	0x0000fc00	/* mask level 2 */
#define SR_IMASK1	0x0000fe00	/* mask level 1 */
#define SR_IMASK0	0x0000ff00	/* mask level 0 */

#define SR_IBIT8	0x00008000	/* bit level 8 */
#define SR_IBIT7	0x00004000	/* bit level 7 */
#define SR_IBIT6	0x00002000	/* bit level 6 */
#define SR_IBIT5	0x00001000	/* bit level 5 */
#define SR_IBIT4	0x00000800	/* bit level 4 */
#define SR_IBIT3	0x00000400	/* bit level 3 */
#define SR_IBIT2	0x00000200	/* bit level 2 */
#define SR_IBIT1	0x00000100	/* bit level 1 */

#define SR_CUMASK	0xf0000000	/* coproc usable bits */

#define SR_CU3		0x80000000	/* Coprocessor 3 usable */
#define SR_CU2		0x40000000	/* Coprocessor 2 usable */
#define SR_CU1		0x20000000	/* Coprocessor 1 usable */
#define SR_CU0		0x10000000	/* Coprocessor 0 usable */

#define SR_SR		0x00100000	/* soft reset occured */
#define SR_CH		0x00040000	/* Cache hit for last 'cache' op */
#define SR_CE		0x00020000	/* Create ECC */
#define SR_DE		0x00010000	/* ECC of parity does not cause error */
#define SR_RP		0x08000000	/* enable reduced-power operation */
#define SR_FR		0x04000000	/* enable additional fp registers */
#define SR_RE		0x02000000	/* reverse endian in user mode */

#define SR_KX		0x00000080	/* extended-addr TLB vec in kernel */
#define SR_SX		0x00000040	/* xtended-addr TLB vec supervisor */
#define SR_UX		0x00000020	/* xtended-addr TLB vec in user mode */
#define SR_KSU_MSK	0x00000018	/* 2 bit mode: 00b=>k, 10b=>u */
#define SR_KSU_USR	0x00000010	/* 2 bit mode: 00b=>k, 10b=>u */