mips_arch.h

一个用在mips体系结构中的操作系统

/*
 * Copyright (C) 1996-1998 by the Board of Trustees
 *    of Leland Stanford Junior University.
 * 
 * This file is part of the SimOS distribution. 
 * See LICENSE file for terms of the license. 
 *
 */

/*****************************************************************
 * mips_arch.h
 *
 * Generic mips architecture definition intended to be shared among
 * simulators. Most of this is taken from sbd.h.
 * 
 * $Author: bosch $
 * $Date: 1998/02/10 00:32:44 $
 *****************************************************************/
#ifndef MIPS_ARCH_H
#define MIPS_ARCH_H

#ifndef _LANGUAGE_ASSEMBLY

/* Has uint, etc */
#include <sys/types.h>
#include "simtypes.h"


#ifdef i386
#undef SP
#endif

/* TLB index register */
typedef Reg32 IndexReg;

/* TLB random register */
typedef Reg32 RandomReg;


/* TLB context register */


#ifdef HOST_BIG_ENDIAN

typedef union tlb_ctxt {
  Reg64 tc_data;               /* efficient access */
  struct {
    unsigned notused;
    unsigned tc_ptebase:9; /* bits 21-31 of kernel pte window */
    unsigned tc_badvpn:19;    /* vpn of faulting ref (ro) */
    unsigned :4;
  }s32;
  struct {
    Reg64 tc_ptebase:41; /* bits 21-63 of kernel pte window */
    Reg64 tc_badvpn:19;    /* vpn of faulting ref (ro) */
    Reg64  :4;
  }s64;
} ContextReg;
#endif
#ifdef HOST_LITTLE_ENDIAN
typedef union tlb_ctxt {
  Reg64 tc_data;               /* efficient access */
  struct {
    unsigned :4;
    unsigned tc_badvpn:19;    /* vpn of faulting ref (ro) */
    unsigned tc_ptebase:9; /* bits 21-31 of kernel pte window */
    unsigned notused;
  }s32;
  struct {
    Reg64 :4;
    Reg64 tc_badvpn:19;    /* vpn of faulting ref (ro) */
    Reg64 tc_ptebase:41; /* bits 21-63 of kernel pte window */
  }s64;
} ContextReg;
#endif

#if defined(sgi) && !defined(_COMPILER_VERSION)
/* The old IRIX 5.3 compilers can't handle the following bit field. */
#define BIG_BIT_FIELD_BROKEN
#endif

#ifdef HOST_BIG_ENDIAN

typedef union tlb_Xctxt {
  Reg64 tc_data;               /* efficient access */
  struct {
    Reg64 tc_ptebase:27; 
    Reg64 tc_region:2;   
#ifndef BIG_BIT_FIELD_BROKEN
    Reg64 tc_badvpn:31;    /* vpn of faulting ref (ro) */
#else
    Reg64 tc_badvpn_hi3:3;   
    Reg64 tc_badvpn_lo28:28;   /* Patch around SGI compiler bug */
#endif
    Reg64 :4;
  }s64;
} XContextReg;
#endif
#ifdef HOST_LITTLE_ENDIAN
typedef union tlb_Xctxt {
  Reg64 tc_data;               /* efficient access */
  struct {
    Reg64 :4;
    Reg64 tc_badvpn:31;    /* vpn of faulting ref (ro) */
    Reg64 tc_region:2;   
    Reg64 tc_ptebase:27;
  }s64;
} XContextReg;
#endif


/* TLB cause Register */
/* typedef Reg CauseReg;*/

#ifdef HOST_BIG_ENDIAN
typedef union {
  Reg32 tc_data;
  struct {
    unsigned tc_bd:1;
    unsigned :1;
    unsigned tc_ce:2;           /* Coprocessor Error - which one */
    unsigned :12;
    unsigned tc_ip:8;           /* Interrupt Pending */
    unsigned :1;
    unsigned tc_exccode:5;      /* Exception code (Table 6-2)
                                   changing to 7 to use sbd's exceptions */
    unsigned :2;
  }s32;
} CauseReg;
#endif
#ifdef HOST_LITTLE_ENDIAN
typedef union {
  Reg32 tc_data;
   struct {
      unsigned :2;
      unsigned tc_exccode:5;      /* Exception code (Table 6-2)
                                     changing to 7 to use sbd's exceptions */
      unsigned :1;
      unsigned tc_ip:8;           /* Interrupt Pending */
      unsigned :12;
      unsigned tc_ce:2;           /* Coprocessor Error - which one */
      unsigned :1;
      unsigned tc_bd:1;
      /* -- */

   }s32;
} CauseReg;
#endif


/* 
 * TLB status register
 */

#ifdef HOST_BIG_ENDIAN

typedef union tlb_status {
  Reg32 ts_data;
  struct {
    unsigned ts_xx:1;           /* Enable MIPS IV opcodes (1 == enabled )*/
    unsigned ts_cu2:1;		/* Usability of coprocessor 2 (1 = usable) */
    unsigned ts_cu1:1;		/* Usability of coprocessor 1 (1 = usable) */
    unsigned ts_cu0:1;		/* Usability of coprocessor 0 (1 = usable) */
    unsigned ts_rp:1;           /* reduce power operation 0=full speed */  
    unsigned ts_fr:1;           /* enable additional fpt regs, 0=16 1=32 */   
    unsigned ts_re:1;           /* reverse endian mode, not currently used*/
    /* diagnostic status fields */
    unsigned ts_dszero:2;       /* Some zeroes in the DS field */
    unsigned ts_bev:1;		/* Location of TLB refill and gen. exception 
				   vectors (0 = normal; 1 = bootstrap) */
    unsigned ts_ts:1;		/* TLB shut-down has occurred. */
    unsigned ts_sr:1;           /* soft reset has occured */   
    unsigned ts_nmi:1;          /* R10000 - nmi occured */
    unsigned ts_ch:1;           /* hit or miss indication of caches */
    unsigned ts_ce:1;           /* ECC controling bit */   
    unsigned ts_de:1;           /*cache parity/ECC errors cause no exceptions*/
    /* end diagnostic status fields */
    unsigned ts_im:8;           /* Interrupt Mask */
    unsigned ts_kx:1;           /* 64 bit in kernel mode */
    unsigned ts_sx:1;           /* 64 bit in supervisor mode */  
    unsigned ts_ux:1;           /* 64 bit in user mode */
    unsigned ts_ksu:2;          /* mode 10=user 01=superv 00=kernel */
    unsigned ts_erl:1;          /* Error level 0=normal */
    unsigned ts_exl:1;          /* Exception level 0=normal */
    unsigned ts_ie:1;           /* interrupt enable 0=disable */
  }s32;
} StatusReg;
#endif


#ifdef HOST_LITTLE_ENDIAN
typedef union tlb_status {
  unsigned ts_data;
  struct {

    unsigned ts_ie:1;           /* interrupt enable 0=disable */
    unsigned ts_exl:1;          /* Exception level 0=normal */
    unsigned ts_erl:1;          /* Error level 0=normal */
    unsigned ts_ksu:2;          /* mode 10=user 01=superv 00=kernel */
    unsigned ts_ux:1;           /* 64 bit in user mode */
    unsigned ts_sx:1;           /* 64 bit in supervisor mode */  
    unsigned ts_kx:1;           /* 64 bit in kernel mode */
    unsigned ts_im:8;           /* Interrupt Mask */
    /* end diagnostic status fields */
    unsigned ts_de:1;           /*cache parity/ECC errors cause no exceptions*/
    unsigned ts_ce:1;           /* ECC controling bit */   
    unsigned ts_ch:1;           /* hit or miss indication of caches */
    unsigned ts_nmi:1;          /* R10000 - nmi occured */
    unsigned ts_sr:1;           /* soft reset has occured */   
    unsigned ts_ts:1;		/* TLB shut-down has occurred. */
    unsigned ts_bev:1;		/* Location of TLB refill and gen. exception 
				   vectors (0 = normal; 1 = bootstrap) */
    unsigned ts_dszero:2;       /* Some zeroes in the DS field */
    /* diagnostic status fields */
    unsigned ts_re:1;           /* reverse endian mode, not currently used*/
    unsigned ts_fr:1;           /* enable additional fpt regs, 0=16 1=32 */   
    unsigned ts_rp:1;           /* reduce power operation 0=full speed */  
    unsigned ts_cu0:1;		/* Usability of coprocessor 0 (1 = usable) */
    unsigned ts_cu1:1;		/* Usability of coprocessor 1 (1 = usable) */
    unsigned ts_cu2:1;		/* Usability of coprocessor 2 (1 = usable) */
    unsigned ts_xx:1;           /* Enable MIPS IV opcodes (1 == enabled )*/
     /*  ------ */
     
  }s32;
} StatusReg;


#endif


typedef Reg EntryHi;           /* Hi part of a TLB Entry */
typedef Reg EntryLo;           /* Lo part of a TLB Entry */
typedef Reg32 EntryPgMsk;        /* Page Mask part of TLB Entry */
typedef struct tlbEntry {       /* Improve caching by pairing these */
   EntryPgMsk PgMsk;
   EntryHi Hi;
   EntryLo Lo0;
   EntryLo Lo1;
} TLBEntry;


/* Zero the field and then or in what is given (with its extra bits chopped off) */
#define CAUSE_SET_EXC(_reg, _code)\
(((uint)(_reg) & (~CAUSE_EXCMASK)) | \
(((uint)(_code) & (CAUSE_EXCMASK>>CAUSE_EXCSHIFT)) << CAUSE_EXCSHIFT))
/* We need this version because the shifted code is passed to EXCEPTION */
#define CAUSE_SET_EXC_NOSHIFT(_reg, _code)\
(((uint)(_reg) & (~CAUSE_EXCMASK)) | ((uint)(_code) & CAUSE_EXCMASK) )
#define CAUSE_SET_CE(_reg, _ce) \
(((uint)(_reg) & (~CAUSE_CEMASK)) | \
(((uint)(_ce) & (CAUSE_CEMASK>>CAUSE_CESHIFT)) << CAUSE_CESHIFT))
#define CAUSE_SET_BD(_reg, _bd) (_bd ? ((_reg) | CAUSE_BD) : \
((_reg) & (~CAUSE_BD)) )


/* Physical Line Number */
typedef Reg32 PLN;

/* K0 Virtual Address */
typedef Reg K0A;

/* Virtual Line Number */
typedef Reg VLN;

/* Virtual Page Number */
typedef Reg VPN;

/* Physical Page Number */
typedef Reg32 PFN;

/* Address Space Identifier */
typedef uint ASID;

#endif /* _LANGUAGE_ASSEMBLY */


#define INST_SIZE    4
#if defined(SIM_MIPS32)
#define REG_SIZE     4
#else
#define REG_SIZE     8
#endif
#define DEFAULT_PAGESZ      4096

#define NUM_GP_REGS  32
#define NUM_CP0_REGS 32
#define NUM_FP_REGS  32
#define NUM_FC_REGS  32

/* This is the hardware clock interrupt and is used to set the correct */
/* bit in the status and cause register */ 
#define CLOCK_INTR_BIT   (1 << 4)

/*
 * The following macros can be used to break apart and join VA and PA
 * addresses.
 */

/* TLB entry manipulation macros */
#define GET_ASID(addr) (((EntryHi)(addr) & TLBHI_PIDMASK) >> TLBHI_PIDSHIFT)
#ifdef notdef
#define GET_VPN(addr)  (((EntryHi)(addr) & TLBHI_VPNMASK) >> TLBHI_VPNSHIFT)
#endif
#define GET_PFN(addr)  (((EntryLo)(addr) & TLBLO_PFNMASK) >> TLBLO_PFNSHIFT)
#define GET_IDX(_idxreg) (((IndexReg)(_idxreg) & TLBINX_INXMASK) >> TLBINX_INXSHIFT)
#define TLBHI2ADDR(_ent) (_ent & TLBHI_VPN2MASK)
#define TLBLO2ADDR(_ent) (GET_PFN(_ent) << NUM_OFFSET_BITS)

#define IS_GLOBAL_HI(_enHi) ((EntryHi)(_enHi) & TLBHI_G)
#define IS_GLOBAL_LO(_enLo) ((EntryLo)(_enLo) & TLBLO_G)
#define CONVERT_TO_VPN2(_addrpfn) ((_addrpfn) >> 1)
#define GET_VPN2(_enHi) (((EntryHi)(_enHi) & TLBHI_VPN2MASK) >> STATIC_VPN2SHIFT)

#define GET_REGION(_enHi) (((Reg_s)(_enHi) >> TLBHI_REGIONSHIFT) & 3)

#define IS_LO_0(_pfn) (!((_pfn) & 1))

#define IS_CACHEABLE(_enLo) !((((EntryLo)(_enLo) & TLBLO_CACHMASK) == TLBLO_UNCACHED) &&   \
                             (((EntryLo)(_enLo) & TLBLO_CACHMASK) == TLBLO_UNCACHED_ACCEL))
#ifdef oldR4000
#define IS_CACHEABLE(_enLo) (((EntryLo)(_enLo) & TLBLO_CACHMASK) != TLBLO_UNCACHED)
#endif

#define GET_CACHE_ALGOR(_enLo) (((EntryLo)(_enLo) & TLBLO_CACHMASK)>>TLBLO_CACHSHIFT)

#define IS_GLOBAL(_en) ((_en) & TLBLO_G)
#define IS_VALID(_en)  ((_en) & TLBLO_V)
#define IS_NC(_en)     ((_en) & TLBLO_N)
#define IS_DIRTY(_en)  ((_en) & TLBLO_D)

#define IS_VALID_AND_CACHEABLE(_en)   (((_en) & TLBLO_V) && !(IS_NC((_en))))

# define NUM_ASID_BITS (8)
#if defined(SIM_MIPS32)
# define NUM_VPN_BITS (20)          /* vAddrs */
#else
# define NUM_VPN2_BITS (VA_VALID_BITS-NUM_OFFSET_BITS)  /* vAddrs */
#endif
# define NUM_OFFSET_BITS (12)       /* eventually not static */

#define NUM_INSTR_BITS  (32)
#define INVALID_ASID    ((1 << NUM_ASID_BITS) + 1)

#define PAGE_OFFSET(_addr)       ((_addr)&((1 << NUM_OFFSET_BITS) - 1))
#define PAGE_NUMBER(_addr)       (((uint)(_addr)) >> NUM_OFFSET_BITS)
#define FORM_ADDR(_pfn, _offset) (((_pfn) << NUM_OFFSET_BITS) | (_offset))


/* Zero the offset and add page */
#define NEXT_PAGE(_addr)         ((((VA)_addr) & (VA)(~(DEFAULT_PAGESZ-1))) + DEFAULT_PAGESZ)

/* Macros to cons up instructions ( ConsInstruction<instruction_type>) */
#define CIi(opCode, rt, rs, immed) ((int)\
((opCode) << 26 | (rs) << 21 | (rt) << 16 | ((immed) & 0xffff ) ) )

#define CIs(funct, rd, rs, rt) ((int)\
(spec_op << 26 | (rs) << 21 | (rt) << 16 | (rd) << 11 | funct) )

/* General Purpose Registers */
#define REG_ZERO   0
#define REG_AT     1
#define REG_V0     2
#define REG_V1     3
#define REG_A0     4
#define REG_A1     5
#define REG_A2     6
#define REG_A3     7
#define REG_T0     8
#define REG_T1     9
#define REG_T2     10
#define REG_T3     11
#define REG_T4     12 
#define REG_T5     13
#define REG_T6     14
#define REG_T7     15
#define REG_S0     16
#define REG_S1     17
#define REG_S2     18
#define REG_S3     19
#define REG_S4     20
#define REG_S5     21
#define REG_S6     22
#define REG_S7     23
#define REG_T8     24
#define REG_T9     25
#define REG_K0     26
#define REG_K1     27
#define REG_GP     28
#define REG_SP     29
#define REG_FP     30
#define REG_S8     30
#define REG_RA     31
#define REG_PC     32