machine_defs.h

一个用在mips体系结构中的操作系统

#define __MAGIC_PPC_OPC_OFFS        __MAGIC_PPC_SEQ_BITS
#define __MAGIC_PPC_GRP_BITS        8
#define __MAGIC_PPC_GRP_OFFS        (__MAGIC_PPC_SEQ_BITS+__MAGIC_PPC_OPC_BITS)

#define __MAGIC_ZONE(node, nbits, zone)                                    \
   ( __MAGIC_BASE | ((node) << __MAGIC_NODE_OFFS)                          \
                  | ((zone) << __MAGIC_ZONE_OFFS) )
#define __MAGIC_ZONE_ACC(node, nbits, zone)                                \
   ( __MAGIC_BASE_ACC | ((node) << __MAGIC_NODE_OFFS)                      \
                      | ((zone) << __MAGIC_ZONE_OFFS) )
#define __MAGIC_ZONE_ALIAS(zone)                                           \
   ( __MAGIC_BASE | ((zone) << __MAGIC_ZONE_OFFS) )
#define __MAGIC_ZONE_ALIAS_ACC(zone)                                       \
   ( __MAGIC_BASE_ACC | ((zone) << __MAGIC_ZONE_OFFS) )
#define __MAGIC_OSPC_RANGE(node, nbits)                                    \
   ( __MAGIC_OSPC_BASE )

#define MAGIC_MAX_REMAP_PAGES       1  /* max. sz of remap area (limited
					* by OSPC in following page) */

/* offsets in bdoor zone of simulated devices (64KB each) */
#define __MAGIC_BDOOR_CLOCK_OFFS        0x00000000 /* CMOS rt clock */
#define __MAGIC_BDOOR_CNSLE_OFFS        0x00001000 /* console interface */
#define __MAGIC_BDOOR_ETHER_OFFS        0x00002000 /* ethernet controller */
#define __MAGIC_BDOOR_DISKS_OFFS        0x00010000 /* scsi disk controller */

#ifdef TORNADO
#define __MAGIC_BDOOR_GIZMO_OFFS	                                      \
    ((__MAGIC_BDOOR_DISKS_OFFS + sizeof(DevDiskRegisters)*DEV_DISK_MAX_UNIT + \
      0x1000 - 1) & ~(0x1000-1))		   /* gizmo interface */
#endif

#else /* SIMOS64BIT */ /* 64 bit address space */
not yet implemented, will not compile;
#endif /* SIMOS64BIT */

#ifdef LANGUAGE_ASSEMBLY
#define MagicRegister int
#define MAGICREGP_CAST
#else
typedef unsigned long long MagicRegister;
#define MAGICREGP_CAST (MagicRegister *)
#endif

/* PPR access */
#define MAGIC_PPR(node, nbits, reg)                                        \
   ((MagicRegister*)                                                       \
    (__MAGIC_ZONE(node,nbits,MAGIC_ZONE_PPR) | ((reg) << __MAGIC_REG_OFFS)))
#define MAGIC_PPR_ALIAS(reg)                                               \
   (MAGICREGP_CAST                                                       \
    (__MAGIC_ZONE_ALIAS(MAGIC_ZONE_PPR_ALIAS) | ((reg) << __MAGIC_REG_OFFS)))
#define MAGIC_PPR_NODE(addr, nbits)                                        \
   ( ((addr) >> __MAGIC_NODE_OFFS) & ((1LL << (nbits)) - 1) )
#define MAGIC_PPR_ZONE(addr)                                               \
   ( ((addr) >> __MAGIC_ZONE_OFFS) & ((1LL << __MAGIC_ZONE_BITS) - 1) )
#define MAGIC_PPR_REG(addr)                                                \
   ( ((addr) >> __MAGIC_REG_OFFS) & ((1LL << __MAGIC_REG_BITS) - 1) )

/* PPC access */
#define MAGIC_PPC(node, nbits, grp, opc)                                   \
   ((MagicRegister*)                                                       \
    ( __MAGIC_ZONE(node,nbits,MAGIC_ZONE_PPC) |                            \
      ((grp) << __MAGIC_PPC_GRP_OFFS) |                                    \
      ((opc) << __MAGIC_PPC_OPC_OFFS) ))
#define MAGIC_PPC_ACC(node, nbits, grp, opc)                               \
   ((MagicRegister*)                                                       \
    ( __MAGIC_ZONE_ACC(node,nbits,MAGIC_ZONE_PPC) |                        \
      ((grp) << __MAGIC_PPC_GRP_OFFS) |                                    \
      ((opc) << __MAGIC_PPC_OPC_OFFS) ))
#define MAGIC_PPC_ALIAS(grp, opc)                                          \
   (MAGICREGP_CAST                                                         \
    ( __MAGIC_ZONE_ALIAS(MAGIC_ZONE_PPC_ALIAS)                             \
                   | ((grp) << __MAGIC_PPC_GRP_OFFS)                       \
                   | ((opc) << __MAGIC_PPC_OPC_OFFS) ))
#ifdef _LANGUAGE_ASSEMBLY
#define MAGIC_PPC_ALIAS_ACC(grp, opc)                                      \
    ( __MAGIC_ZONE_ALIAS_ACC(MAGIC_ZONE_PPC_ALIAS)                         \
                   | ((grp) << __MAGIC_PPC_GRP_OFFS)                       \
                   | ((opc) << __MAGIC_PPC_OPC_OFFS) )

#else /* ASS */
#define MAGIC_PPC_ALIAS_ACC(grp, opc)                                      \
   ((MagicRegister*)                                                       \
    ( __MAGIC_ZONE_ALIAS_ACC(MAGIC_ZONE_PPC_ALIAS)                         \
                   | ((grp) << __MAGIC_PPC_GRP_OFFS)                       \
                   | ((opc) << __MAGIC_PPC_OPC_OFFS) ))
#endif /* ASS */

#define MAGIC_PPC_NODE(addr,nbits)                                         \
   ( ((addr) >> __MAGIC_NODE_OFFS) & ((1LL << (nbits)) - 1) )
#define MAGIC_PPC_ZONE(addr)                                               \
   ( ((addr) >> __MAGIC_ZONE_OFFS) & ((1LL << __MAGIC_ZONE_BITS) - 1) )
#define MAGIC_PPC_GRP(addr)                                                \
   ( ((addr) >> __MAGIC_PPC_GRP_OFFS) & ((1LL << __MAGIC_PPC_GRP_BITS) - 1) )
#define MAGIC_PPC_OPC(addr)                                                \
   ( ((addr) >> __MAGIC_PPC_OPC_OFFS) & ((1LL << __MAGIC_PPC_OPC_BITS) - 1) )

/* Nodemap access */
#define MAGIC_NODEMAP(node, nbits, reg)                                    \
   ((MagicRegister*)                                                       \
    (__MAGIC_ZONE(node,nbits,MAGIC_ZONE_NODEMAP) | ((reg) << __MAGIC_REG_OFFS)))

/* Nodecomm access */
#define MAGIC_NODECOMM(node, nbits, n)                                     \
   ((MagicRegister*)                                                       \
    (__MAGIC_ZONE(node,nbits,MAGIC_ZONE_NODECOMM) | ((n) << __MAGIC_REG_OFFS)))

/* OSPC access */
#define MAGIC_OSPC(node, nbits, ospc)                                      \
   ( (MagicRegister*)(__MAGIC_OSPC_RANGE(node, nbits) + (ospc)) )

#define MAGIC_UNCACHED_OSPC(node, nbits, offs)                             \
   MAGIC_PPR(node, nbits, MAGIC_PPR_OSPC + ((offs) >> __MAGIC_REG_OFFS))

#define MAGIC_UNCACHED_OSPC_ALIAS(offs)                                    \
   MAGIC_PPR_ALIAS(MAGIC_PPR_OSPC + ((offs) >> __MAGIC_REG_OFFS))

/* firewall access */
#define MAGIC_FW_RANGE(node, nbits)                                        \
   ((MagicRegister*) __MAGIC_ZONE(node,nbits,MAGIC_ZONE_FIREWALL))


/***************************************************************************
 definitions of the simulated devices and of various parameters
 which depend on the simulator.
 ***************************************************************************/

#define MAGIC_MAX_CPUS                32 /* max no of nodes in a simulation */
#define MAGIC_MAX_CELLS               32 /* max no of cells in a simulation */


/* needed so assembly files can include machine_defs */
#ifndef LANGUAGE_ASSEMBLY

#ifdef _KERNEL
#if defined(_MIPS3_ADDRSPACE) || defined(_K64U64)
/* Origin2000 running M-Mode assumes node size is 32bits,
 which happens to match flash's notion with nnbits=8 */
#define MAGIC_NODE_SIZE_BITS            32
#define MAGIC_NODE_OFFSET_MASK          ((1LL << MAGIC_NODE_SIZE_BITS) - 1)
typedef unsigned long long DevRegister;
#else
typedef unsigned int DevRegister;
#endif
#else /* _KERNEL */
#ifdef SIM_MIPS64
#define MAGIC_NODE_SIZE_BITS            32
#define MAGIC_NODE_OFFSET_MASK          ((1LL << MAGIC_NODE_SIZE_BITS) - 1)
typedef unsigned long long DevRegister;
#else
typedef unsigned int DevRegister;
#endif
#endif /* _KERNEL */

/* disk device:
 * there is currently one controller per cell. The controller
 * can be accessed through the backdoor zone of the first node
 * in the cell.
 */

#define DEV_DISK_CMD_SIZE            12
#define DEV_DISK_MAX_DMA_LENGTH      1024 /* max no of pages for one request */
#define DEV_DISK_MAX_UNIT            128  /* max disks per node. Note the disks
					   * might be attached to different
					   * controllers.
					   */

typedef struct DevDiskRegisters {
    DevRegister intr_pending;     /* r:int posted for this disk / w:ack int */
    DevRegister errnoVal;         /* status of last i/o */
    DevRegister bytesTransferred; /* bytes transferred during last i/o */

    DevRegister interruptNode;    /* node to interrupt upon completion */
    DevRegister k0Addr[DEV_DISK_MAX_DMA_LENGTH]; /* page addresses */
    DevRegister offset;           /* page offset for first page */
    DevRegister command[DEV_DISK_CMD_SIZE]; /* i/o command */

    DevRegister startIO;          /* write here causes i/o initiation */
    DevRegister doneIO;           /* tells when i/o complete */

    DevRegister filler[16];       /* filler: resize when you add new regs */
} DevDiskRegisters;

#define DEV_DISK_REGISTERS(node, nbits, unit)                         \
   ( ((volatile DevDiskRegisters*)                                    \
        (__MAGIC_ZONE(node, nbits, MAGIC_ZONE_BDOOR_DEV) +            \
         __MAGIC_BDOOR_DISKS_OFFS)) +                                 \
     (unit) )


/* console device:
 * there is currently one console per cell. The console registers
 * can be accessed through the backdoor zone of the first node
 * in the cell. The console always interrupts this node.
 */

#define DEV_CNSLE_TX_INTR            0x01 /* intr enable / state bits */
#define DEV_CNSLE_RX_INTR            0x02

typedef struct DevConsoleRegisters {
    DevRegister intr_status;      /* r: intr state / w: intr enable */
    DevRegister data;             /* r: current char / w: send char */
} DevConsoleRegisters;
 
#define DEV_CONSOLE_REGISTERS(node, nbits)                                  \
   ( ((volatile DevConsoleRegisters*)                                       \
        (__MAGIC_ZONE(node, nbits, MAGIC_ZONE_BDOOR_DEV) +                  \
         __MAGIC_BDOOR_CNSLE_OFFS)) )


/* ethernet device:
 * there is currently one ether interface per cell. The ether registers
 * can be accessed through the backdoor zone of the first node
 * in the cell. The ether interface always interrupts this node.
 */

#define DEV_ETHER_MAX_RCV_ENTRIES    64
#define DEV_ETHER_MAX_SND_ENTRIES    64
#define DEV_ETHER_MAX_SND_CHUNKS     128

#define DEV_ETHER_MAX_TRANSFER_SIZE  1800

typedef struct DevEtherRegisters {
  DevRegister etheraddr[6];       /* controller tells OS its ethernet addr */
  DevRegister numRcvEntries;      /* read by OS, indicates how many receive
				   * ring buffer entries will be used. OS must
				   * allocate a receive buffer for each of
				   * these entries */
  DevRegister numSndEntries;      /* read by OS, indicates how many send ring
				   * buffer entries will be used so it knows
				   * when to wrap its index pointer */
  DevRegister numSndChunks;       /* same as numSndEntries */

  struct {
    DevRegister pAddr;
    DevRegister maxLen;
    DevRegister len;
    DevRegister flag;         
  } rcvEntries[ DEV_ETHER_MAX_RCV_ENTRIES ];

  struct {
    DevRegister firstChunk;
    DevRegister lastChunk;
    DevRegister flag; /* triggers send */
  } sndEntries[ DEV_ETHER_MAX_SND_ENTRIES ];

  struct { 
    DevRegister pAddr;
    DevRegister len;
  } sndChunks[ DEV_ETHER_MAX_SND_CHUNKS ]; 

  /* note: sndChunks is last because we might extend the number of
   * send chunks in the future and don't want to break OS compatibility when
   * we do it */
} DevEtherRegisters;

/* values for flag field */
#define DEV_ETHER_OS_OWNED           (DevRegister)1
#define DEV_ETHER_CONTROLLER_OWNED   (DevRegister)2

#define DEV_ETHER_REGISTERS(node, nbits)                                  \
   ( ((volatile DevEtherRegisters*)                                       \
        (__MAGIC_ZONE(node, nbits, MAGIC_ZONE_BDOOR_DEV) +                \
         __MAGIC_BDOOR_ETHER_OFFS)) )


/* CMOS RT clock device:
 * This simulates a very primitive CMOS clock. This device only
 * has one register that contains the time since January 1, 1970
 * (same as the Unix gettimeofday() result).
 */

typedef struct DevClockRegisters {
  DevRegister ctime;              /* current time */
} DevClockRegisters;

#define DEV_CLOCK_REGISTERS(node, nbits)                                  \
   ( ((volatile DevClockRegisters*)                                       \
        (__MAGIC_ZONE(node, nbits, MAGIC_ZONE_BDOOR_DEV) +                \
         __MAGIC_BDOOR_CLOCK_OFFS)) )


#endif /* LANGUAGE_ASSEMBLY */


/* Interrupt bit assignments:
 *
 * There are 64 external interrupt lines coming into MAGIC. The
 * following defines show to what interrupt line each device is
 * connected.
 *
 * NOTE: when MAGIC posts an interrupt, the IEChigh register will
 * contain the bit number of the highest level interrupt pending,
 * so the bit numbers are also IEC's (Interrupt Exception Codes).
 */

#define DEV_IEC_SCSI                0x08    /* scsi disk controller */
#define DEV_IEC_ETHER               0x09    /* ether controller */
#define DEV_IEC_OSPC_LO             0x0a    /* low-priority SIPS */
#define DEV_IEC_VEC_REQ             0x0b    /* vector packet request */
#define DEV_IEC_KEYBDMOUSE          0x10    /* console */
#define DEV_IEC_DUART               0x11    /* serial line on FLASH board */
#define DEV_IEC_OSPC_HI             0x12    /* high-priority SIPS */
#define DEV_IEC_RECOVERY            0x13    /* recov int (posted by MAGIC) */
#define DEV_IEC_VEC_REPLY           0x14    /* vector packet reply */
#define DEV_IEC_MIG_REP             0x17    /* page migration hot page */
#define DEV_IEC_CLOCK               0x18    /* clock */
#define DEV_IEC_IPI                 0x20    /* inter-processor interrupt (level 0)*/
#define DEV_IEC_DEBUG               0x21    /* ??? */
#define DEV_IEC_IPI1                 0x22    /* inter-processor interrupt (level 1)*/
#define DEV_IEC_IPI2                 0x23    /* inter-processor interrupt (level 2)*/
#define DEV_IEC_PROFTIM             0x28    /* prof timer (currently unused) */
#define DEV_IEC_MAGICWARN           0x29    /* ??? */
#define DEV_IEC_MAGICERR            0x31    /* ??? */
#define DEV_IEC_POWERFAIL           0x38    /* ??? */

#define DEV_IEC_MAX                 0x3f    /* 64 bits */


/* PCI slot assignments:
 *
 * NOTE:
 * On the real system these slot assignments wouldn't be fixed (you
 * could plug a card into any slot on the I/O bus) but this isn't
 * particularly interesting to model.
 */

#define DEV_PCI_DISK_SLOT           0
#define DEV_PCI_ETHER_SLOT          1
#define DEV_PCI_CONSOLE_SLOT        2


#endif /* _MACHINE_DEFS_H */