params.c

一个用在mips体系结构中的操作系统

      FIRST_MEMORY(machNo) = memoryCount;
      memoryCount += NUM_MEMORIES(machNo);
      LAST_MEMORY(machNo) = memoryCount-1;

      FIRST_CONSOLE(machNo) = consoleCount;
      consoleCount += NUM_CONSOLES(machNo);
      LAST_CONSOLE(machNo) = consoleCount-1;
      if (NUM_CONSOLES(machNo) > MAX_CONSOLES_PER_MACHINE)
         MAX_CONSOLES_PER_MACHINE = NUM_CONSOLES(machNo);

      FIRST_ETHER_CONTROLLER(machNo) = etherCount;
      etherCount += NUM_ETHER_CONTROLLERS(machNo);
      LAST_ETHER_CONTROLLER(machNo) = etherCount-1;
      if (NUM_ETHER_CONTROLLERS(machNo) > MAX_ETHER_CONTROLLERS_PER_MACHINE)
         MAX_ETHER_CONTROLLERS_PER_MACHINE = NUM_ETHER_CONTROLLERS(machNo);

      FIRST_CLOCK(machNo) = clockCount;
      clockCount += NUM_CLOCKS(machNo);
      LAST_CLOCK(machNo) = clockCount-1;
      if (NUM_CLOCKS(machNo) > MAX_CLOCKS_PER_MACHINE)
         MAX_CLOCKS_PER_MACHINE = NUM_CLOCKS(machNo);

#if !defined(SOLO) && (defined(SIM_MIPS32) || defined(SIM_MIPS64))
      machines.machine[machNo].CPUsPerCell = machines.machine[machNo].NumCPUs /
                                             machines.machine[machNo].NumCells;
      machines.machine[machNo].log2CPUsPerCell =
                                 GetLog2(machines.machine[machNo].NumCPUs /
                                         machines.machine[machNo].NumCells);
#else
#ifdef SIM_ALPHA
      machines.machine[machNo].CPUsPerCell = -12345678;   /* unused */
      machines.machine[machNo].log2CPUsPerCell = -12345678; /* unused */
#else
      machines.machine[machNo].CPUsPerCell = machines.machine[machNo].NumCPUs;
      machines.machine[machNo].log2CPUsPerCell =
                                 GetLog2(machines.machine[machNo].CPUsPerCell);
#endif
#endif

   }
   machines.TotalCPUs = cpuCount;
   machines.TotalMemories = memoryCount;
   machines.TotalConsoles = consoleCount;
   machines.TotalEtherControllers = etherCount;
   machines.TotalClocks = clockCount;

   machines.SCacheSize = machines.SCacheSizeSpecified*1024;
   machines.ICacheSize = machines.ICacheSizeSpecified*1024;
   machines.DCacheSize = machines.DCacheSizeSpecified*1024;

   machines.PerfectMemLatency = 
                          NanoSecsToCycles(machines.PerfectMemLatencySpecified);
   machines.MemCycleTime = NanoSecsToCycles(machines.MemCycleTimeSpecified);
   machines.UpgradeTime  = NanoSecsToCycles(machines.UpgradeTimeSpecified);
   machines.DirtyPenalty = NanoSecsToCycles(machines.DirtyPenaltySpecified);
#ifndef SOLO
   machines.SIPSLatency  = NanoSecsToCycles(machines.SIPSLatencySpecified);
   machines.IPILatency   = NanoSecsToCycles(machines.IPILatencySpecified);
   if (machines.InitialTimeSpecified == 0) {
      int ret; struct timeval tv;
      /* An InitialTime of zero means use current time. */
      ret = gettimeofday(&tv, NULL);
      ASSERT(ret == 0);
      machines.InitialTime  = tv.tv_sec;
   } else {
      machines.InitialTime = machines.InitialTimeSpecified;
   }
#endif
   machines.log2ICacheLineSize = GetLog2(machines.ICacheLineSize);
   machines.log2ICacheSize     = GetLog2(machines.ICacheSize);
   machines.log2ICacheAssoc    = GetLog2(machines.ICacheAssoc);

   machines.iCacheIndex = machines.ICacheSize 
      / machines.ICacheLineSize 
      / machines.ICacheAssoc;

   machines.log2DCacheLineSize = GetLog2(machines.DCacheLineSize);
   machines.log2DCacheSize     = GetLog2(machines.DCacheSize);
   machines.log2DCacheAssoc    = GetLog2(machines.DCacheAssoc);

   machines.dCacheIndex = machines.DCacheSize 
      / machines.DCacheLineSize 
      / machines.DCacheAssoc;

   machines.SCacheHitTime      = (machines.SCacheHitTimeSpecified 
                                * machines.CpuClock ) / 1000;  
   machines.log2SCacheSize     = GetLog2(machines.SCacheSize);
   machines.log2SCacheLineSize = GetLog2(machines.SCacheLineSize);
   machines.log2SCacheAssoc    = GetLog2(machines.SCacheAssoc);

   machines.sCacheIndex = machines.SCacheSize 
      / machines.SCacheLineSize 
      / machines.SCacheAssoc;

   machines.NumaBusTime   = NanoSecsToCycles(machines.NumaBusTimeSpecified);
   machines.NumaPILocalDCTime  = NanoSecsToCycles(machines.NumaPILocalDCTimeSpecified);
   machines.NumaPIRemoteDCTime = NanoSecsToCycles(machines.NumaPIRemoteDCTimeSpecified);
   machines.NumaNILocalDCTime  = NanoSecsToCycles(machines.NumaNILocalDCTimeSpecified);
   machines.NumaNIRemoteDCTime = NanoSecsToCycles(machines.NumaNIRemoteDCTimeSpecified);
   machines.NumaMemTime   = NanoSecsToCycles(machines.NumaMemTimeSpecified);
   machines.NumaNetTime   = NanoSecsToCycles(machines.NumaNetTimeSpecified);

   DumpMachineParams();
}

/*****************************************************************
 * SetAdditionalParams
 *****************************************************************/
void
SetAdditionalParams(Tcl_Interp *interp)
{
   int machineCount, totalCpuCount, cpuCount;
   
   Tcl_SetVar2(interp, "PARAM", "MACHINE.TotalCPUs",
               tcl_itoa(machines.TotalCPUs), TCL_GLOBAL_ONLY);
   
   for (machineCount = 0, totalCpuCount = 0;
        machineCount < machines.NumMachines; machineCount++) {
      for (cpuCount = 0; cpuCount < machines.machine[machineCount].NumCPUs;
           cpuCount++) {
         Tcl_SetVar2(interp, "M", tcl_itoa(totalCpuCount),
                    tcl_itoa(machineCount), TCL_GLOBAL_ONLY);
         Tcl_SetVar2(interp, "MCPU", tcl_itoa(totalCpuCount),
                    tcl_itoa(cpuCount), TCL_GLOBAL_ONLY);
         totalCpuCount++;
      }
   }
}

/*****************************************************************
 *
 * CPU Model is handled specially because it can be overriden
 * on the command line.
 *
 *****************************************************************/

static int CPUTypeSpecified = 0;

void InitCPUModel(CPUType cmdLineCPU)
{
   if (cmdLineCPU != NO_CPU) {
      CPUTypeSpecified = 1;
      ParamGrabbedAtStartup("PARAM(CPU.Model)");
   }
   
   simosCPUType = cmdLineCPU;

   if (simosCPUType == EMBRA_PAGE) {
      machines.CpuModel = SaveString("EMBRA_PAGE");
   } else if (simosCPUType == EMBRA_CACHE) {
      machines.CpuModel = SaveString("EMBRA_CACHE");
   } else if (simosCPUType == MIPSY) {
      machines.CpuModel = SaveString("MIPSY");
#if defined(SIM_ALPHA)
   } else if (simosCPUType == GAMMA) {
      machines.CpuModel = SaveString("GAMMA");
   } else if (simosCPUType == DELTA) { 
      machines.CpuModel = SaveString("DELTA");
   } else if (simosCPUType == EPSILON) { 
      machines.CpuModel = SaveString("EPSILON");
   } else if (simosCPUType == KAPPA) { 
      machines.CpuModel = SaveString("KAPPA");
#endif
   } else if (simosCPUType == NO_CPU) {
      machines.CpuModel = SaveString("NONE");
   } else {
      ASSERT(0);
   }   
}

char *AccessCPUModel(Tcl_Interp *interp)
{
   if (CPUTypeSpecified) {
      free(machines.CpuModel);
      
#if defined(SIM_MIPS32) || defined(SIM_MIPS64)
      if (simosCPUType == EMBRA_PAGE) {
         Tcl_SetVar2(interp, "PARAM", "CPU.Model", "EMBRA_PAGE", TCL_GLOBAL_ONLY);
         machines.CpuModel = SaveString("EMBRA_PAGE");
      } else if (simosCPUType == EMBRA_CACHE) {
         Tcl_SetVar2(interp, "PARAM", "CPU.Model", "EMBRA_CACHE", TCL_GLOBAL_ONLY);
         machines.CpuModel = SaveString("EMBRA_CACHE");
      } else if (simosCPUType == MIPSY) {
         Tcl_SetVar2(interp, "PARAM", "CPU.Model", "MIPSY", TCL_GLOBAL_ONLY);
         machines.CpuModel = SaveString("MIPSY");
      } else
#endif /* def SIM_MIPS32 || def SIM_MIPS64 */
#ifdef SIM_ALPHA
      if (simosCPUType == GAMMA) {
         Tcl_SetVar2(interp, "PARAM", "CPU.Model", "GAMMA", TCL_GLOBAL_ONLY);
         machines.CpuModel = SaveString("GAMMA");
      } else if (simosCPUType==DELTA) { 
         Tcl_SetVar2(interp, "PARAM", "CPU.Model", "DELTA", TCL_GLOBAL_ONLY);
         machines.CpuModel = SaveString("DELTA");	 
      } else if (simosCPUType==EPSILON) { 
         Tcl_SetVar2(interp, "PARAM", "CPU.Model", "EPSILON", TCL_GLOBAL_ONLY);
         machines.CpuModel = SaveString("EPSILON");	 
      } else if (simosCPUType==KAPPA) { 
         Tcl_SetVar2(interp, "PARAM", "CPU.Model", "KAPPA", TCL_GLOBAL_ONLY);
         machines.CpuModel = SaveString("KAPPA");	 
      } else
#endif /* def SIM_ALPHA */
#ifdef SIM_X86
      if (simosCPUType == X86SIM) { 
         Tcl_SetVar2(interp, "PARAM", "CPU.Model", "X86SIM", TCL_GLOBAL_ONLY);
         machines.CpuModel = SaveString("X86SIM");
      } else
#endif /* def SIM_X86 */
         ASSERT(0);
      
   } else {
      char *model = Tcl_GetVar2(interp, "PARAM", "CPU.Model", TCL_GLOBAL_ONLY);

#if defined(SIM_MIPS32) || defined(SIM_MIPS64)
      if (strcmp("EMBRA_PAGE", model) == 0) { 
         simosCPUType = EMBRA_PAGE;
      } else if (strcmp("EMBRA_CACHE", model) == 0) { 
         simosCPUType = EMBRA_CACHE;
      } else if (strcmp("MIPSY", model) == 0) { 
         simosCPUType = MIPSY;
      } else if (strcmp("MXS", model) == 0) { 
         simosCPUType = MIPSY;
      } else
#endif /* def SIM_MIPS32 || def SIM_MIPS64 */
#ifdef SIM_ALPHA
      if (strcmp("GAMMA", model) == 0) { 
         simosCPUType = GAMMA;
      } else if (strcmp("DELTA",model)==0) {
	 simosCPUType = DELTA;
      } else if (strcmp("EPSILON",model)==0) {
	 simosCPUType = EPSILON;
      } else if (strcmp("KAPPA",model)==0) {
	 simosCPUType = KAPPA;
      } else
#endif /* def SIM_ALPHA */
#ifdef SIM_X86
      if (strcmp("X86SIM", model) == 0) { 
         simosCPUType = X86SIM;
      } else
#endif /* def SIM_X86 */
         return "unknown cpu model";
   }

   return NULL;
} /* AccessCPUModel () */


/*****************************************************************
 * DumpMachineParams
 *****************************************************************/
static void
DumpMachineParams(void)
{
   int machNo;
   int node;
   
   CPUPrint("=============================================================\n");
   CPUPrint("=                   MACHINE PARAMETERS                      =\n");
   CPUPrint("=============================================================\n");

   CPUPrint("\nNumber of machines = %d\n", machines.NumMachines);

   for (machNo = 0; machNo < NUM_MACHINES; machNo++) { 
      CPUPrint("\n===== Machine %d =====\n\n", machNo);
      CPUPrint("MACHINE NumCPUs\t\t\t%d\n", machines.machine[machNo].NumCPUs);
      CPUPrint("MACHINE NumCells\t\t%d\n", machines.machine[machNo].NumCells);
      CPUPrint("MACHINE MemSize\t\t\t%d  Meg\n", machines.machine[machNo].MemSizeSpecified);
      CPUPrint("MACHINE NumMemories\t\t%d\n", machines.machine[machNo].NumMemories);

#if !defined(SOLO) && (defined(SIM_MIPS32) || defined(SIM_MIPS64))
      if (!strcmp(machines.machine[machNo].DiskModel, "HP")) {
         CPUPrint("MACHINE DiskModel\t\tHP\n");
         CPUPrint("MACHINE DiskScaling\t\t%d %%\n",  machines.machine[machNo].HPDiskScaling);
      } else {
         CPUPrint("MACHINE DiskModel\t\tFixed\n");
         CPUPrint("MACHINE FixedDiskDelay\t\t%d ns\n",  machines.machine[machNo].FixedDiskDelay);
      }
#endif

      CPUPrint("MACHINE NumConsoles\t\t%d\n",  machines.machine[machNo].NumConsoles);
      CPUPrint("MACHINE NumEtherInterfaces\t%d\n",  machines.machine[machNo].NumEtherControllers);

#if !defined(SOLO)
      CPUPrint("MACHINE NumUnitsPerController\t\t%d ns\n",
	       machines.machine[machNo].NumUnitsPerController);
      /* DT: disk controllers are now per node */
      for (node = 0; node < NUM_CPUS(machNo); node++) {
	CPUPrint("MACHINE NumDiskControllers.%d\t%d\n",
		 node, machines.machine[machNo].NumDiskCtrls[node]);
      }
#endif

      CPUPrint("MACHINE NumClocks\t\t%d\n",  machines.machine[machNo].NumClocks);
   }

   CPUPrint("\n===== Additional params for all machines =====\n\n");

   CPUPrint("MACHINE BusBW\t\t%d MB/s\n", machines.BusBW);
   CPUPrint("MACHINE Clock\t\t%d Mhz\n", machines.CpuClock);

   CPUPrint("MACHINE DCacheSize\t%d kB\n",  machines.DCacheSizeSpecified);
   CPUPrint("MACHINE DCacheAssoc\t%d way\n",  machines.DCacheAssoc);
   CPUPrint("MACHINE DCacheLineSize\t%d bytes\n",  machines.DCacheLineSize);

   CPUPrint("MACHINE DirtyPenalty\t%d ns\n", machines.DirtyPenaltySpecified);

   CPUPrint("MACHINE ICacheAssoc\t%d way\n",  machines.ICacheAssoc);
   CPUPrint("MACHINE ICacheLineSize\t%d bytes\n",  machines.ICacheLineSize);
   CPUPrint("MACHINE ICacheSize\t%d kB\n",  machines.ICacheSizeSpecified);

   CPUPrint("MACHINE PerfectMemLatency\t%d ns\n", 
            machines.PerfectMemLatencySpecified);

   CPUPrint("MACHINE MemCycleTime\t%d ns\n", machines.MemCycleTimeSpecified);

   CPUPrint("MACHINE SCacheAssoc\t%d way\n",  machines.SCacheAssoc);
   CPUPrint("MACHINE SCacheHitTime\t%d ns\n",  machines.SCacheHitTimeSpecified);
   CPUPrint("MACHINE SCacheLineSize\t%d bytes\n",  machines.SCacheLineSize);
   CPUPrint("MACHINE SCacheSize\t%d kB\n",  machines.SCacheSizeSpecified);
   CPUPrint("MACHINE NAKRetryTime\t%d cycles\n", machines.NAKRetryTime);

#ifndef SOLO
   CPUPrint("MACHINE SIPSLatency\t%d ns\n", machines.SIPSLatencySpecified);
   CPUPrint("MACHINE IPILatency\t%d ns\n", machines.IPILatencySpecified);
   CPUPrint("MACHINE InitialTime\t%d ns\n", machines.InitialTimeSpecified);
#endif

   CPUPrint("MACHINE UpgradeTime\t%d ns\n", machines.UpgradeTimeSpecified);

   CPUPrint("MACHINE WriteBufferSize\t%d entries\n",  machines.WriteBufferSize);

   CPUPrint("MACHINE NumaBusTime\t%d entries\n",  machines.NumaBusTimeSpecified);
   CPUPrint("MACHINE NumaPILocalDCTime\t%d entries\n",  machines.NumaPILocalDCTimeSpecified);
   CPUPrint("MACHINE NumaPIRemoteDCTime\t%d entries\n", machines.NumaPIRemoteDCTimeSpecified);
   CPUPrint("MACHINE NumaNILocalDCTime\t%d entries\n",  machines.NumaNILocalDCTimeSpecified);
   CPUPrint("MACHINE NumaNIRemoteDCTime\t%d entries\n", machines.NumaNIRemoteDCTimeSpecified);
   CPUPrint("MACHINE NumaMemTime\t%d entries\n",  machines.NumaMemTimeSpecified);
   CPUPrint("MACHINE NumaNetTime\t%d entries\n",  machines.NumaNetTimeSpecified);
   CPUPrint("MACHINE NumaStripeSize\t%d entries\n",  machines.NumaStripeSize);

   CPUPrint("\n=============================================================\n\n");
}