📄 amir_1.abl
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module amir_1
OUT_CLOCK PIN 67;
IN_CLOCK PIN 72;
CLK_GATE PIN 73;
_OUTPUT PIN 74;
INPUT_2 PIN 76;
INPUT_1 PIN 78;
INPUT_0 PIN 80;
tdo PIN 6; "TDO
tdi PIN 7; "TDI
tck PIN 16; "TCK
tms PIN 20; "TMS
ale PIN 4; "ALE output
a11 PIN 57; "Address line
a10 PIN 55; "Address line
a9 PIN 53; "Address line
a8 PIN 51; "Address line
a7 PIN 47; "Data/address bus line
a6 PIN 45; "Data/address bus line
a5 PIN 43; "Data/address bus line
a4 PIN 41; "Data/address bus line
a3 PIN 39; "Data/address bus line
a2 PIN 38; "Data/address bus line
a1 PIN 37; "Data/address bus line
a0 PIN 36; "Data/address bus line
Reset_In PIN 68;
VREF PIN 70; "VREF input
_rd PIN 62;
_psen PIN 63;
_wr PIN 65;
USB_minus PIN 8; "USB- bus
USB_plus PIN 10; "USB+ bus
Xtal1 PIN 48; "Xtal1
Xtal2 PIN 49; "Xtal2
rs0 node;
csiop node;
fs0 node;
fs1 node;
csboot0 node;
csboot1 node;
csboot2 node;
csboot3 node;
_reset node 543;
a12 node 512;
a13 node 513;
a14 node 514;
a15 node 515;
HALF_CLOCK NODE istype 'reg_D';
SIGNAL_X NODE;
X = .x.;
address = [a15..a0];
Vcc = 1;
Gnd = 0;
// Begin user preserved declarations (not affected by iterations of DA usage) ===================
// End user preserved declarations (not affected by iterations of DA usage) ===================
equations
rs0 = ((address >= ^h0000) & (address <= ^h1FFF));
csiop = ((address >= ^hA000) & (address <= ^hA0FF));
fs0 = ((address >= ^h0000) & (address <= ^h7FFF));
fs1 = ((address >= ^h8000) & (address <= ^hFFFF));
csboot0 = ((address >= ^h2000) & (address <= ^h3FFF));
csboot1 = ((address >= ^h4000) & (address <= ^h5FFF));
csboot2 = ((address >= ^h6000) & (address <= ^h7FFF));
csboot3 = ((address >= ^h8000) & (address <= ^h9FFF));
OUT_CLOCK = CLK_GATE & HALF_CLOCK;
_OUTPUT = !(SIGNAL_X & INPUT_2);
HALF_CLOCK := !HALF_CLOCK;
HALF_CLOCK.ck = IN_CLOCK;
HALF_CLOCK.re = !_reset;
HALF_CLOCK.pr = Gnd;
SIGNAL_X = INPUT_0 # INPUT_1;
// Begin user preserved equations (not affected by iterations of DA usage) ===================
// End user preserved equations (not affected by iterations of DA usage) ===================
end amir_1
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