amir_1.sum

UPSD3200系列单片机CPLD逻辑功能C51开发包代码!

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                         PSDsoft Express Version 7.80
                         Summary of Design Assistant
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PROJECT    : amir_1                        DATE : 01/08/2003
DEVICE     : uPSD3234A                     TIME : 17:21:57
MCU/DSP    : uPSD32XX    
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Initial setting for Program and Data Space:
===========================================

  Main PSD flash memory will reside in this space at power-up:      Program Space Only
  Secondary PSD flash memory will reside in this space at power-up: Data Space Only

Pin Definitions:
================

Pin          Signal                    Pin
Name         Name                      Type
------------ ------------------------- ------------
pb6          OUT_CLOCK                 Combinatorial
pb5          IN_CLOCK                  Logic or address
pb4          CLK_GATE                  Logic or address
pb3          _OUTPUT                   Combinatorial
pb2          INPUT_2                   Logic or address
pb1          INPUT_1                   Logic or address
pb0          INPUT_0                   Logic or address
tdo          tdo                       Dedicated JTAG - TDO
tdi          tdi                       Dedicated JTAG - TDI
tck          tck                       Dedicated JTAG - TCK
tms          tms                       Dedicated JTAG - TMS
ale          ale                       ALE output  
a11          a11                       Address line
a10          a10                       Address line
a9           a9                        Address line
a8           a8                        Address line
ad7          a7                        Data/Address line
ad6          a6                        Data/Address line
ad5          a5                        Data/Address line
ad4          a4                        Data/Address line
ad3          a3                        Data/Address line
ad2          a2                        Data/Address line
ad1          a1                        Data/Address line
ad0          a0                        Data/Address line
Reset_In     Reset_In                  Reset In    
Vref         VREF                      VREF input  
_rd          _rd                       Bus control output
_psen        _psen                     Bus control output
_wr          _wr                       Bus control output
USB-         USB_minus                 USB- bus    
USB+         USB_plus                  USB+ bus    
Xtal1        Xtal1                     Xtal1       
Xtal2        Xtal2                     Xtal2       

User defined nodes:
===================

Node         Node
Name         Type
------------ ------------
HALF_CLOCK   D-type register
SIGNAL_X     Combinatorial

Page Register settings:
=======================

pgr0 is not used
pgr1 is not used
pgr2 is not used
pgr3 is not used
pgr4 is not used
pgr5 is not used
pgr6 is not used
pgr7 is not used

Equations:
==========

rs0 = ((address >= ^h0000) & (address <= ^h1FFF));
csiop = ((address >= ^hA000) & (address <= ^hA0FF));
fs0 = ((address >= ^h0000) & (address <= ^h7FFF));
fs1 = ((address >= ^h8000) & (address <= ^hFFFF));
csboot0 = ((address >= ^h2000) & (address <= ^h3FFF));
csboot1 = ((address >= ^h4000) & (address <= ^h5FFF));
csboot2 = ((address >= ^h6000) & (address <= ^h7FFF));
csboot3 = ((address >= ^h8000) & (address <= ^h9FFF));
OUT_CLOCK = CLK_GATE & HALF_CLOCK;
_OUTPUT = !(SIGNAL_X & INPUT_2);
HALF_CLOCK := !HALF_CLOCK;
HALF_CLOCK.ck = IN_CLOCK;
HALF_CLOCK.re = !_reset;
HALF_CLOCK.pr = Gnd;
SIGNAL_X = INPUT_0 # INPUT_1;