📄 disasm.c

📁 一个很好的嵌入式linux平台下的bootloader
💻 C
📖 第 1 页 / 共 5 页
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 {"nmadd.s"       , DC_FD_FR_FS_FT },  {"nmadd.d"       , DC_FD_FR_FS_FT },  {"invalid"       , DC_BARE        },  {"invalid"       , DC_BARE        },  {"invalid"       , DC_BARE        },  {"invalid"       , DC_BARE        },  {"nmadd.ps"      , DC_FD_FR_FS_FT },  {"invalid"       , DC_BARE        },  {"nmsub.s"       , DC_FD_FR_FS_FT },  {"nmsub.d"       , DC_FD_FR_FS_FT },  {"invalid"       , DC_BARE        },  {"invalid"       , DC_BARE        },  {"invalid"       , DC_BARE        },  {"invalid"       , DC_BARE        },  {"nmsub.ps"      , DC_FD_FR_FS_FT },  {"invalid"       , DC_BARE        }};static const disasm_t disasm_mdmx[8] DATASEG = {{ "$20"      , DC_DEREF       }, { "$19"      , DC_DEREF       }, { "$20"      , DC_DEREF       }, { "$33"      , DC_DEREF       }, { "$20"      , DC_DEREF       }, { "$19"      , DC_DEREF       }, { "$20"      , DC_DEREF       }, { "$33"      , DC_DEREF       },};static const disasm_t disasm_mdmx_qh[64] DATASEG = {{ "msgn.qh"      , DC_VD_VS_VT_VEC}, { "c.eq.qh"      , DC_VS_VT_VEC   }, { "pickf.qh"     , DC_VD_VS_VT_VEC}, { "pickt.qh"     , DC_VD_VS_VT_VEC}, { "c.lt.qh"      , DC_VS_VT_VEC   }, { "c.le.qh"      , DC_VS_VT_VEC   }, { "min.qh"       , DC_VD_VS_VT_VEC}, { "max.qh"       , DC_VD_VS_VT_VEC}, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "sub.qh"       , DC_VD_VS_VT_VEC}, { "add.qh"       , DC_VD_VS_VT_VEC}, { "and.qh"       , DC_VD_VS_VT_VEC}, { "xor.qh"       , DC_VD_VS_VT_VEC}, { "or.qh"        , DC_VD_VS_VT_VEC}, { "nor.qh"       , DC_VD_VS_VT_VEC}, { "sll.qh"       , DC_VD_VS_VT_VEC}, { "invalid"      , DC_BARE        }, { "srl.qh"       , DC_VD_VS_VT_VEC}, { "sra.qh"       , DC_VD_VS_VT_VEC}, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "alni.ob"      , DC_VD_VS_VT_IMM}, { "alnv.ob"      , DC_VD_VS_VT_RS }, { "alni.qh"      , DC_VD_VS_VT_IMM}, { "alnv.qh"      , DC_VD_VS_VT_RS }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "$34"      , DC_DEREF       }, { "rzu.qh"       , DC_VD_VT       }, { "rnau.qh"      , DC_VD_VT       }, { "rneu.qh"      , DC_VD_VT       }, { "invalid"      , DC_BARE        }, { "rzs.qh"       , DC_VD_VT       }, { "rnas.qh"      , DC_VD_VT       }, { "rnes.qh"      , DC_VD_VT       }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "mul.qh"       , DC_VD_VS_VT_VEC}, { "invalid"      , DC_BARE        }, { "$21"      , DC_DEREF       }, { "$22"      , DC_DEREF       }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "$23"      , DC_DEREF       }, { "$24"      , DC_DEREF       }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "$25"      , DC_DEREF       }, { "$26"      , DC_DEREF       },};static const disasm_t disasm_mdmx_ob[64] DATASEG = {{ "invalid"      , DC_BARE        }, { "c.eq.ob"      , DC_VS_VT_VEC   }, { "pickf.ob"     , DC_VD_VS_VT_VEC}, { "pickt.ob"     , DC_VD_VS_VT_VEC}, { "c.lt.ob"      , DC_VS_VT_VEC   }, { "c.le.ob"      , DC_VS_VT_VEC   }, { "min.ob"       , DC_VD_VS_VT_VEC}, { "max.ob"       , DC_VD_VS_VT_VEC}, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "sub.ob"       , DC_VD_VS_VT_VEC}, { "add.ob"       , DC_VD_VS_VT_VEC}, { "and.ob"       , DC_VD_VS_VT_VEC}, { "xor.ob"       , DC_VD_VS_VT_VEC}, { "or.ob"        , DC_VD_VS_VT_VEC}, { "nor.ob"       , DC_VD_VS_VT_VEC}, { "sll.ob"       , DC_VD_VS_VT_VEC}, { "invalid"      , DC_BARE        }, { "srl.ob"       , DC_VD_VS_VT_VEC}, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "alni.ob"      , DC_VD_VS_VT_IMM}, { "alnv.ob"      , DC_VD_VS_VT_RS }, { "alni.qh"      , DC_VD_VS_VT_IMM}, { "alnv.qh"      , DC_VD_VS_VT_RS }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "$35"      , DC_DEREF       }, { "rzu.ob"       , DC_VD_VT       }, { "rnau.ob"      , DC_VD_VT       }, { "rneu.ob"      , DC_VD_VT       }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "mul.ob"       , DC_VD_VS_VT_VEC}, { "invalid"      , DC_BARE        }, { "$27"      , DC_DEREF       }, { "$28"      , DC_DEREF       }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "$29"      , DC_DEREF       }, { "$30"      , DC_DEREF       }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "$31"      , DC_DEREF       }, { "$32"      , DC_DEREF       },};static const disasm_t disasm_mdmx_alni[64] DATASEG = {{ "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "alni.ob"      , DC_VD_VS_VT_IMM}, { "alnv.ob"      , DC_VD_VS_VT_RS }, { "alni.qh"      , DC_VD_VS_VT_IMM}, { "alnv.qh"      , DC_VD_VS_VT_RS }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        },};static const disasm_t disasm_mdmx_muls_qh[2] DATASEG = {{ "muls.qh"      , DC_VS_VT_VEC   }, { "mulsl.qh"     , DC_VS_VT_VEC   },};static const disasm_t disasm_mdmx_mul_qh[2] DATASEG = {{ "mula.qh"      , DC_VS_VT_VEC   }, { "mull.qh"      , DC_VS_VT_VEC   },};static const disasm_t disasm_mdmx_sub_qh[2] DATASEG = {{ "suba.qh"      , DC_VS_VT_VEC   }, { "subl.qh"      , DC_VS_VT_VEC   },};static const disasm_t disasm_mdmx_add_qh[2] DATASEG ={{ "adda.qh"      , DC_VS_VT_VEC   }, { "addl.qh"      , DC_VS_VT_VEC   },};static const disasm_t disasm_mdmx_wac_qh[4] DATASEG = {{ "wacl.qh"      , DC_VS_VT       }, { "invalid"      , DC_BARE        }, { "wach.qh"      , DC_VS          }, { "invalid"      , DC_BARE        },};static const disasm_t disasm_mdmx_rac_qh[4] DATASEG = {{ "racl.qh"      , DC_VD          }, { "racm.qh"      , DC_VD          }, { "rach.qh"      , DC_VD          }, { "invalid"      , DC_BARE        },};static const disasm_t disasm_mdmx_muls_ob[2] DATASEG = {{ "muls.ob"      , DC_VS_VT_VEC   }, { "mulsl.ob"     , DC_VS_VT_VEC   },};static const disasm_t disasm_mdmx_mul_ob[2] DATASEG = {{ "mula.ob"      , DC_VS_VT_VEC   }, { "mull.ob"      , DC_VS_VT_VEC   },};static const disasm_t disasm_mdmx_sub_ob[2] DATASEG = {{ "suba.ob"      , DC_VS_VT_VEC   }, { "subl.ob"      , DC_VS_VT_VEC   },};static const disasm_t disasm_mdmx_add_ob[2] DATASEG ={{ "adda.ob"      , DC_VS_VT_VEC   }, { "addl.ob"      , DC_VS_VT_VEC   },};static const disasm_t disasm_mdmx_wac_ob[4] DATASEG = {{ "wacl.ob"      , DC_VS_VT       }, { "invalid"      , DC_BARE        }, { "wach.ob"      , DC_VS          }, { "invalid"      , DC_BARE        },};static const disasm_t disasm_mdmx_rac_ob[4] DATASEG = {{ "racl.ob"      , DC_VD          }, { "racm.ob"      , DC_VD          }, { "rach.ob"      , DC_VD          }, { "invalid"      , DC_BARE        },};static const disasm_t disasm_mdmx_shfl_ob[16] DATASEG = {{ "shfl.upsl.ob" , DC_VD_VS_VT    }, { "shfl.pach.ob" , DC_VD_VS_VT    }, { "shfl.mixh.ob" , DC_VD_VS_VT    }, { "shfl.mixl.ob" , DC_VD_VS_VT    }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        },};static const disasm_t disasm_mdmx_shfl_qh[8] DATASEG =  {{ "shfl.bfla.qh" , DC_VD_VS_VT    }, { "shfl.pach.qh" , DC_VD_VS_VT    }, { "shfl.mixh.qh" , DC_VD_VS_VT    }, { "shfl.mixl.qh" , DC_VD_VS_VT    }, { "shfl.repa.qh" , DC_VD_VS_VT    }, { "shfl.repb.qh" , DC_VD_VS_VT    }, { "invalid"      , DC_BARE        }, { "invalid"      , DC_BARE        },};const disasm_deref_t disasm_deref[] = /* Disasm array           shft   msk */{{ disasm_normal      ,     26, 0x3f },   /*  0 */ { disasm_special     ,      0, 0x3f },   /*  1 */ { disasm_regimm      ,     16, 0x1f },   /*  2 */ { disasm_spec2       ,      0, 0x3f },   /*  3 */ { disasm_cop0        ,     21, 0x1f },   /*  4 */ { disasm_cop0_c0     ,      0, 0x3f },   /*  5 */ { disasm_cop1        ,     21, 0x1f },   /*  6 */ { disasm_cop1_s      ,      0, 0x3f },   /*  7 */ { disasm_cop1_s_mvcf ,     16,  0x1 },   /*  8 */ { disasm_cop1_d      ,      0, 0x3f },   /*  9 */ { disasm_cop1_d_mvcf ,     16,  0x1 },   /* 10 */ { disasm_cop1_w      ,      0, 0x3f },   /* 11 */ { disasm_cop1_l      ,      0, 0x3f },   /* 12 */ { disasm_cop1_ps     ,      0, 0x3f },   /* 13 */ { disasm_cop1_ps_mvcf,     16,  0x1 },   /* 14 */ { disasm_cop1x       ,      0, 0x3f },   /* 15 */ { disasm_movci       ,     16,  0x1 },   /* 16 */ { disasm_cop1_bc1    ,     16,  0x3 },   /* 17 */ { disasm_mdmx        ,     21,  0x7 },   /* 18 */ { disasm_mdmx_qh     ,      0, 0x3f },   /* 19 */ { disasm_mdmx_ob     ,      0, 0x3f },   /* 20 */ { disasm_mdmx_muls_qh,     10,  0x1 },   /* 21 */ { disasm_mdmx_mul_qh ,     10,  0x1 },   /* 22 */ { disasm_mdmx_sub_qh ,     10,  0x1 },   /* 23 */ { disasm_mdmx_add_qh ,     10,  0x1 },   /* 24 */ { disasm_mdmx_wac_qh ,     24,  0x3 },   /* 25 */ { disasm_mdmx_rac_qh ,     24,  0x3 },   /* 26 */ { disasm_mdmx_muls_ob,     10,  0x1 },   /* 27 */ { disasm_mdmx_mul_ob ,     10,  0x1 },   /* 28 */ { disasm_mdmx_sub_ob ,     10,  0x1 },   /* 29 */ { disasm_mdmx_add_ob ,     10,  0x1 },   /* 30 */ { disasm_mdmx_wac_ob ,     24,  0x3 },   /* 31 */ { disasm_mdmx_rac_ob ,     24,  0x3 },   /* 32 */ { disasm_mdmx_alni   ,      0, 0x3f },   /* 33 */ { disasm_mdmx_shfl_ob,     22,  0xf },   /* 34 */ { disasm_mdmx_shfl_qh,     23,  0x7 },   /* 35 */ { disasm_cop1_bc1any2,     16,  0x1 },   /* 36 */ { disasm_cop1_bc1any4,     16,  0x1 },   /* 37 */ { disasm_cop1_c_f_s  ,      6,  0x1 },   /* 38 */ { disasm_cop1_c_un_s ,      6,  0x1 },   /* 39 */ { disasm_cop1_c_eq_s ,      6,  0x1 },   /* 40 */ { disasm_cop1_c_ueq_s,      6,  0x1 },   /* 41 */ { disasm_cop1_c_olt_s,      6,  0x1 },   /* 42 */ { disasm_cop1_c_ult_s,      6,  0x1 },   /* 43 */ { disasm_cop1_c_ole_s,      6,  0x1 },   /* 44 */ { disasm_cop1_c_ule_s,      6,  0x1 },   /* 45 */ { disasm_cop1_c_sf_s ,      6,  0x1 },   /* 46 */ { disasm_cop1_c_ngle_s,     6,  0x1 },   /* 47 */
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