disasm.c

一个很好的嵌入式linux平台下的bootloader

/*  *********************************************************************
    *  Broadcom Common Firmware Environment (CFE)
    *  
    *  MIPS disassembler		    	File: disasm.c
    *  
    *  MIPS disassembler (used by ui_examcmds.c)
    *  
    *  Author:  Justin Carlson
    *  
    *********************************************************************  
    *
    *  Copyright 2000,2001,2002,2003
    *  Broadcom Corporation. All rights reserved.
    *  
    *  This software is furnished under license and may be used and 
    *  copied only in accordance with the following terms and 
    *  conditions.  Subject to these conditions, you may download, 
    *  copy, install, use, modify and distribute modified or unmodified 
    *  copies of this software in source and/or binary form.  No title 
    *  or ownership is transferred hereby.
    *  
    *  1) Any source code used, modified or distributed must reproduce 
    *     and retain this copyright notice and list of conditions 
    *     as they appear in the source file.
    *  
    *  2) No right is granted to use any trade name, trademark, or 
    *     logo of Broadcom Corporation.  The "Broadcom Corporation" 
    *     name may not be used to endorse or promote products derived 
    *     from this software without the prior written permission of 
    *     Broadcom Corporation.
    *  
    *  3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
    *     IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
    *     WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
    *     PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 
    *     SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 
    *     PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
    *     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 
    *     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
    *     GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
    *     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 
    *     OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 
    *     TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 
    *     THE POSSIBILITY OF SUCH DAMAGE.
    ********************************************************************* */


#include "lib_types.h"
#include "lib_string.h"
#include "disasm.h"
#include "lib_printf.h"

#define UINT64_T(x) ((uint64_t) (x))
#define PF_64 "ll"
#define PF_32 ""
/* These aren't guaranteed to be portable, either */
#define SEXT_32(bit, val) \
			   ((((int32_t)(val))<<(31-(bit)))>>(31-(bit)))
#define SEXT_64(bit, val) \
			   ((((int64_t)(val))<<(63-(bit)))>>(63-(bit)))

#define DATASEG __attribute__ ((section(".text")))


#define REGNAME(r) (&_regnames[(r)*5])
static const char * const _regnames =
    "zero\0"
    "AT\0  "
    "v0\0  "
    "v1\0  "
    "a0\0  "
    "a1\0  "
    "a2\0  "
    "a3\0  "
    "t0\0  "
    "t1\0  "
    "t2\0  "
    "t3\0  "
    "t4\0  "
    "t5\0  "
    "t6\0  "
    "t7\0  "
    "s0\0  "
    "s1\0  "
    "s2\0  "
    "s3\0  "
    "s4\0  "
    "s5\0  "
    "s6\0  "
    "s7\0  "
    "t8\0  "
    "t9\0  "
    "k0\0  "
    "k1\0  "
    "gp\0  "
    "sp\0  "
    "fp\0  "
    "ra\0  ";	

#define CP0REGNAME(r) (&_cp0names[(r)*12])
static const char * const _cp0names =
    "C0_INX\0     "
    "C0_RAND\0    "
    "C0_TLBLO0\0  "
    "C0_TLBLO1\0  "
    	
    "C0_CTEXT\0   "
    "C0_PGMASK\0  "
    "C0_WIRED\0   "
    "C0_reserved\0"
    
    "C0_BADVADDR\0"
    "C0_COUNT\0   "
    "C0_TLBHI\0   "
    "C0_COMPARE\0 "
    
    "C0_SR\0      "
    "C0_CAUSE\0   "
    "C0_EPC\0     "
    "C0_PRID\0    "
    	
    "C0_CONFIG\0  "
    "C0_LLADDR\0  "
    "C0_WATCHLO\0 "
    "C0_WATCHHI\0 "
    
    "C0_XCTEXT\0  "
    "C0_reserved\0"
    "C0_reserved\0"
    "C0_reserved\0"
    
    "C0_reserved\0"
    "C0_reserved\0"
    "C0_reserved\0"
    "C0_reserved\0"
    
    "C0_TAGLO\0   "
    "C0_TAGHI\0   "
    "C0_ERREPC\0  "
    "C0_reserved\0";



/*
 * MIPS instruction set disassembly module.  
 */

typedef enum {
	DC_RD_RS_RT,
	DC_RD_RT_RS,
	DC_RT_RS_SIMM,
	DC_RT_RS_XIMM,
	DC_RS_RT_OFS,
	DC_RS_OFS,
	DC_RD_RT_SA,
	DC_RT_UIMM,
	DC_RD,
	DC_J,
	DC_RD_RS,
	DC_RS_RT,
	DC_RT_RS,
	DC_RT_RD_SEL,
	DC_RT_CR_SEL,
	DC_RS,
	DC_RS_SIMM,
	DC_RT_OFS_BASE,
	DC_FT_OFS_BASE,
	DC_FD_IDX_BASE,
	DC_FS_IDX_BASE,
	DC_FD_FS_FT,
	DC_FD_FS_RT,
	DC_FD_FS,
	DC_PREF_OFS,
	DC_PREF_IDX,
	DC_CC_OFS,
	DC_FD_FS_CC,
	DC_RD_RS_CC,
	DC_FD_FR_FS_FT,
	DC_FD_FS_FT_RS,
	DC_CC_FS_FT,
	DC_BARE,
	DC_RT_FS,
	DC_SYSCALL,
	DC_BREAK,
	DC_VD_VS_VT_VEC,
	DC_VD_VS_VT,
	DC_VS_VT,
	DC_VS_VT_VEC,
	DC_VD_VS_VT_RS,
	DC_VD_VS_VT_IMM,
	DC_VD_VT,
	DC_VD,
	DC_VS,
	DC_DEREF,
	DC_OOPS
} DISASM_CLASS;




/* We're pulling some trickery here.  Most of the time, this structure operates
   exactly as one would expect.  The special case, when type == DC_DREF, 
   means name points to a byte that is an index into a dereferencing array.  */

/*
 * To make matters worse, the whole module has been coded to reduce the 
 * number of relocations present, so we don't actually store pointers
 * in the dereferencing array.  Instead, we store fixed-width strings
 * and use digits to represent indicies into the deref array.
 *
 * This is all to make more things fit in the relocatable version,
 * since every initialized pointer goes into our small data segment.
 */

typedef struct {
    char name[15];
    char type;
} disasm_t;

typedef struct {
	const disasm_t *ptr;
	int shift;
	uint32_t mask;
} disasm_deref_t;
		
/* Forward declaration of deref array, we need this for the disasm_t definitions */


extern const disasm_deref_t disasm_deref[];

static const disasm_t disasm_normal[64] DATASEG = 
{{"$1"        , DC_DEREF       }, 
 {"$2"        , DC_DEREF       }, 
 {"j"             , DC_J           }, 
 {"jal"           , DC_J           },
 {"beq"           , DC_RS_RT_OFS   }, 
 {"bne"           , DC_RS_RT_OFS   }, 
 {"blez"          , DC_RS_OFS      }, 
 {"bgtz"          , DC_RS_OFS      },
 {"addi"          , DC_RT_RS_SIMM  }, 
 {"addiu"         , DC_RT_RS_SIMM  }, 
 {"slti"          , DC_RT_RS_SIMM  }, 
 {"sltiu"         , DC_RT_RS_SIMM  },
 {"andi"          , DC_RT_RS_XIMM  }, 
 {"ori"           , DC_RT_RS_XIMM  }, 
 {"xori"          , DC_RT_RS_XIMM  }, 
 {"lui"           , DC_RT_UIMM     },
 {"$4"        , DC_DEREF       }, 
 {"$6"        , DC_DEREF       }, 
 {"invalid"       , DC_BARE        }, 
 {"$15"       , DC_DEREF       },
 {"beql"          , DC_RS_RT_OFS   }, 
 {"bnel"          , DC_RS_RT_OFS   }, 
 {"blezl"         , DC_RS_OFS      }, 
 {"bgtzl"         , DC_RS_OFS      },
 {"daddi"         , DC_RT_RS_SIMM  }, 
 {"daddiu"        , DC_RT_RS_SIMM  }, 
 {"ldl"           , DC_RT_OFS_BASE }, 
 {"ldr"           , DC_RT_OFS_BASE },
 {"$3"        , DC_DEREF       }, 
 {"invalid"       , DC_BARE        }, 
 {"$18"       , DC_DEREF       }, 
 {"invalid"       , DC_BARE        },
 {"lb"            , DC_RT_OFS_BASE }, 
 {"lh"            , DC_RT_OFS_BASE }, 
 {"lwl"           , DC_RT_OFS_BASE }, 
 {"lw"            , DC_RT_OFS_BASE },
 {"lbu"           , DC_RT_OFS_BASE }, 
 {"lhu"           , DC_RT_OFS_BASE }, 
 {"lwr"           , DC_RT_OFS_BASE }, 
 {"lwu"           , DC_RT_OFS_BASE },
 {"sb"            , DC_RT_OFS_BASE }, 
 {"sh"            , DC_RT_OFS_BASE }, 
 {"swl"           , DC_RT_OFS_BASE }, 
 {"sw"            , DC_RT_OFS_BASE },
 {"sdl"           , DC_RT_OFS_BASE }, 
 {"sdr"           , DC_RT_OFS_BASE }, 
 {"swr"           , DC_RT_OFS_BASE }, 
 {"cache"         , DC_BARE        },
 {"ll"            , DC_RT_OFS_BASE }, 
 {"lwc1"          , DC_FT_OFS_BASE }, 
 {"invalid"       , DC_BARE        }, 
 {"pref"          , DC_PREF_OFS    },
 {"lld"           , DC_RT_OFS_BASE }, 
 {"ldc1"          , DC_FT_OFS_BASE }, 
 {"invalid"       , DC_BARE        }, 
 {"ld"            , DC_RT_OFS_BASE },
 {"sc"            , DC_RT_OFS_BASE }, 
 {"swc1"          , DC_FT_OFS_BASE }, 
 {"invalid"       , DC_BARE        }, 
 {"invalid"       , DC_BARE        },
 {"scd"           , DC_RT_OFS_BASE }, 
 {"sdc1"          , DC_FT_OFS_BASE }, 
 {"invalid"       , DC_BARE        }, 
 {"sd"            , DC_RT_OFS_BASE }};

static const disasm_t disasm_special[64] DATASEG = 
{{"sll"           , DC_RD_RT_SA    }, 
 {"$16"       , DC_DEREF       }, 
 {"srl"           , DC_RD_RT_SA    }, 
 {"sra"           , DC_RD_RT_SA    },
 {"sllv"          , DC_RD_RT_RS    }, 
 {"invalid"       , DC_BARE        }, 
 {"srlv"          , DC_RD_RT_RS    }, 
 {"srav"          , DC_RD_RT_RS    },
 {"jr"            , DC_RS          }, 
 {"jalr"          , DC_RD_RS       }, 
 {"movz"          , DC_RD_RS_RT    }, 
 {"movn"          , DC_RD_RS_RT    },
 {"syscall"       , DC_SYSCALL     }, 
 {"break"         , DC_BREAK       }, 
 {"invalid"       , DC_BARE        }, 
 {"sync"          , DC_BARE        },
 {"mfhi"          , DC_RD          }, 
 {"mthi"          , DC_RS          }, 
 {"mflo"          , DC_RD          }, 
 {"mtlo"          , DC_RS          },
 {"dsllv"         , DC_RD_RT_RS    }, 
 {"invalid"       , DC_BARE        }, 
 {"dsrlv"         , DC_RD_RT_RS    }, 
 {"dsrav"         , DC_RD_RT_RS    },
 {"mult"          , DC_RS_RT       }, 
 {"multu"         , DC_RS_RT       }, 
 {"div"           , DC_RS_RT       }, 
 {"divu"          , DC_RS_RT       },
 {"dmult"         , DC_RS_RT       }, 
 {"dmultu"        , DC_RS_RT       }, 
 {"ddiv"          , DC_RS_RT       }, 
 {"ddivu"         , DC_RS_RT       },
 {"add"           , DC_RD_RS_RT    }, 
 {"addu"          , DC_RD_RS_RT    }, 
 {"sub"           , DC_RD_RS_RT    }, 
 {"subu"          , DC_RD_RS_RT    },
 {"and"           , DC_RD_RS_RT    }, 
 {"or"            , DC_RD_RS_RT    }, 
 {"xor"           , DC_RD_RS_RT    }, 
 {"nor"           , DC_RD_RS_RT    },
 {"invalid"       , DC_BARE        }, 
 {"invalid"       , DC_BARE        }, 
 {"slt"           , DC_RD_RS_RT    }, 
 {"sltu"          , DC_RD_RS_RT    },
 {"dadd"          , DC_RD_RS_RT    }, 
 {"daddu"         , DC_RD_RS_RT    }, 
 {"dsub"          , DC_RD_RS_RT    }, 
 {"dsubu"         , DC_RD_RS_RT    },
 {"tge"           , DC_RS_RT       }, 
 {"tgeu"          , DC_RS_RT       }, 
 {"tlt"           , DC_RS_RT       }, 
 {"tltu"          , DC_RS_RT       },
 {"teq"           , DC_RS_RT       }, 
 {"invalid"       , DC_BARE        }, 
 {"tne"           , DC_RS_RT       }, 
 {"invalid"       , DC_BARE        },
 {"dsll"          , DC_RD_RT_SA    }, 
 {"invalid"       , DC_BARE        }, 
 {"dsrl"          , DC_RD_RT_SA    }, 
 {"dsra"          , DC_RD_RT_SA    },
 {"dsll32"        , DC_RD_RT_SA    }, 
 {"invalid"       , DC_BARE        }, 
 {"dsrl32"        , DC_RD_RT_SA    }, 
 {"dsra32"        , DC_RD_RT_SA    }};

static const disasm_t disasm_movci[2] DATASEG = 
{{"movf"          , DC_RD_RS_CC    },
 {"movt"          , DC_RD_RS_CC    }};

static const disasm_t disasm_regimm[32] DATASEG = 
{{"bltz"          , DC_RS_OFS      }, 
 {"bgez"          , DC_RS_OFS      }, 
 {"bltzl"         , DC_RS_OFS      }, 
 {"bgezl"         , DC_RS_OFS      },
 {"invalid"       , DC_BARE        }, 
 {"invalid"       , DC_BARE        }, 
 {"invalid"       , DC_BARE        }, 
 {"invalid"       , DC_BARE        },
 {"tgei"          , DC_RS_SIMM     }, 
 {"tgeiu"         , DC_RS_SIMM     }, 
 {"tlti"          , DC_RS_SIMM     }, 
 {"tltiu"         , DC_RS_SIMM     },
 {"teqi"          , DC_RS_SIMM     }, 
 {"invalid"       , DC_BARE        }, 
 {"tnei"          , DC_RS_SIMM     }, 
 {"invalid"       , DC_BARE        },
 {"bltzal"        , DC_RS_OFS      }, 
 {"bgezal"        , DC_RS_OFS      }, 
 {"bltzall"       , DC_RS_OFS      }, 
 {"bgezall"       , DC_RS_OFS      },
 {"invalid"       , DC_BARE        }, 
 {"invalid"       , DC_BARE        }, 
 {"invalid"       , DC_BARE        }, 
 {"invalid"       , DC_BARE        },
 {"invalid"       , DC_BARE        }, 
 {"invalid"       , DC_BARE        }, 
 {"invalid"       , DC_BARE        }, 
 {"invalid"       , DC_BARE        },
 {"invalid"       , DC_BARE        }, 
 {"invalid"       , DC_BARE        }, 
 {"invalid"       , DC_BARE        }, 
 {"invalid"       , DC_BARE     }};